參數(shù)資料
型號: P89LPC9381FDH
廠商: NXP Semiconductors N.V.
元件分類: 8位微控制器
英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB 3 V byte-erasable flash with 10-bit ADC
封裝: P89LPC9381FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<Always Pb-free,;
文件頁數(shù): 25/59頁
文件大?。?/td> 286K
代理商: P89LPC9381FDH
P89LPC9381_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 8 September 2006
31 of 60
Philips Semiconductors
P89LPC9381
8-bit microcontroller with 10-bit ADC
7.21 SPI
The P89LPC9381 provides another high-speed serial communication interface—the SPI
interface. SPI is a full-duplex, high-speed, synchronous communication bus with two
operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in either
Master or Slave mode. It has a Transfer Completion Flag and Write Collision Flag
Protection.
The SPI interface has four pins: SPICLK, MOSI, MISO and SS:
SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data ows from master to slave on MOSI (Master Out Slave In) pin and ows
from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output
in the master mode and is input in the slave mode. If the SPI system is disabled, i.e.,
SPEN (SPCTL.6) = 0 (reset value), these pins are congured for port functions.
SS is the optional slave select pin. In a typical conguration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave device
uses its SS pin to determine whether it is selected.
Typical connections are shown in Figure 10 through Figure 12.
Fig 9.
SPI block diagram
002aac552
CPU clock
DIVIDER
BY 4, 16, 64, 128
SELECT
CLOCK LOGIC
SPI CONTROL REGISTER
READ DATA BUFFER
8-BIT SHIFT REGISTER
SPI CONTROL
SPI STATUS REGISTER
SPR1
SPIF
WCOL
SPR0
SPI clock (master)
PIN
CONTROL
LOGIC
S
M
S
M
S
MISO
P2[3]
MOSI
P2[2]
SPICLK
P2[5]
SS
P2[4]
SPI
interrupt
request
internal
data
bus
SSIG
SPEN
MSTR
DORD
MSTR
CPHA
CPOL
SPR1
SPR0
MSTR
SPEN
clock
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