參數(shù)資料
型號: P89LPC936
廠商: NXP Semiconductors N.V.
元件分類: 8位微控制器
英文描述: 8-BIT SINGLE CHIP MICROCONTROLLERS
中文描述: 8位單晶片微控制器
文件頁數(shù): 43/75頁
文件大?。?/td> 372K
代理商: P89LPC936
9397 750 15113
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 06 — 20 June 2005
43 of 75
Philips Semiconductors
P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
8.22 SPI
The P89LPC933/934/935/936 provides another high-speed serial communication
interface—the SPI interface. SPI is a full-duplex, high-speed, synchronous communication
bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be
supported in Master mode or up to 2 Mbit/s in Slave mode. It has a Transfer Completion
Flag and Write Collision Flag Protection.
The SPI interface has four pins: SPICLK, MOSI, MISO and SS:
SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows
from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output
in the master mode and is input in the slave mode. If the SPI system is disabled, i.e.,
SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave device
uses its SS pin to determine whether it is selected.
Typical connections are shown in
Figure 18
through
Figure 20
.
Fig 17. SPI block diagram
002aaa900
CPU clock
DIVIDER
BY 4, 16, 64, 128
SELECT
CLOCK LOGIC
SPI CONTROL REGISTER
READ DATA BUFFER
8-BIT SHIFT REGISTER
SPI CONTROL
SPI STATUS REGISTER
S
S
W
S
SPI clock (master)
PIN
CONTROL
LOGIC
S
M
S
M
M
S
MISO
P2.3
MOSI
P2.2
SPICLK
P2.5
SS
P2.4
SPI
interrupt
request
internal
data
bus
S
S
S
M
D
M
C
C
S
S
MSTR
SPEN
clock
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