- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1959 > P89LPC9351FA,112 (NXP Semiconductors)IC 80C51 MCU FLASH 8K 28-PLCC PDF資料下載
參數(shù)資料
| 型號(hào)： | P89LPC9351FA,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 41/94頁 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 8K 28-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | LPC9351/9321 Overview |
| 標(biāo)準(zhǔn)包裝： | 2,368 |
| 系列： | LPC900 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 18MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 26 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 512 x 8 |
| RAM 容量： | 768 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x8b; D/A 2x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-PLCC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1014-ND - BOARD FOR LPC9XX TSSOP 622-1006-ND - SOCKET ADAPTER BOARD 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART 568-3510-ND - DEMO BOARD SPI/I2C TO UART 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X 568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY |
| 其它名稱： | 568-4701-5 935287627112 P89LPC9351FA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁當(dāng)前第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁
P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5.1 — 20 August 2012
46 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
7.23.7 Break detect
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the device
and force the device into ISP mode.
7.23.8 Double buffering
The UART has a transmit double buffer that allows buffering of the next character to be
written to SnBUF while the first character is being transmitted. Double buffering allows
transmission of a string of characters with only one stop bit between any two characters,
as long as the next character is written between the start bit and the stop bit of the
previous character.
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is
compatible with the conventional 80C51 UART. If enabled, the UART allows writing to
SBUF while the previous data is being shifted out. Double buffering is only allowed in
Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled
(DBMOD = 0).
7.23.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the TI interrupt is generated
when the double buffer is ready to receive new data.
7.23.10 The 9th bit (bit 8) in double buffering (modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as long
as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until
the bit is shifted out, as indicated by the TI interrupt.
If double buffering is enabled, TB must be updated before SBUF is written, as TB8 will be
double-buffered together with SBUF data.
7.24 I2C-bus serial interface
The I2C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features:
Bidirectional data transfer between masters and slaves
Multi master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I2C-bus may be used for test and diagnostic purposes.
device provides a byte-oriented I2C-bus interface that supports data transfers up to
400 kHz.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P89LPC936FDH,518 | IC 80C51 MCU FLASH 16K 28TSSOP |
| P89LPC938FDH,529 | IC 80C51 MCU FLASH 8K 28-TSSOP |
| P89LPC9401FBD,557 | IC 80C51 MCU FLASH 8K 64-LQFP |
| P89LPC9402FBD,557 | IC 80C51 MCU FLASH 8K 64-LQFP |
| P89LPC954FBD44,151 | IC 80C51 MCU FLASH 16K 44LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P89LPC9351FDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 8-bit ADC |
| P89LPC9351FDH,518 | 功能描述:8位微控制器 -MCU Enhanced LPC935 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89LPC935FA | 制造商:NXP Semiconductors 功能描述:IC MCU 8BIT 80C51 8K FLASH PLCC28 |
| P89LPC935FA,129 | 功能描述:8位微控制器 -MCU 80C51 8K FL 768B RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89LPC935FA129 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 18MHZ LCC-28 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。