參數(shù)資料
型號： P89LPC9351FA,112
廠商： NXP Semiconductors
文件頁數(shù)： 39/94頁
文件大?。?/td> 0K
描述： IC 80C51 MCU FLASH 8K 28-PLCC
產(chǎn)品培訓(xùn)模塊： LPC9351/9321 Overview
標(biāo)準(zhǔn)包裝： 2,368
系列： LPC900
核心處理器： 8051
芯體尺寸： 8-位
速度： 18MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 26
程序存儲器容量： 8KB（8K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b; D/A 2x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-PLCC
包裝： 管件
產(chǎn)品目錄頁面： 706 (CN2011-ZH PDF)
配用： 622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱： 568-4701-5
935287627112
P89LPC9351FA
P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5.1 — 20 August 2012
44 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
Since N ranges from 0 to 15, the CCLK frequency can be in the range of PCLK to
PCLK/16.
7.22.9 CCU interrupts
There are seven interrupt sources on the CCU which share a common interrupt vector.
7.23 UART
The P89LPC9331/9341/9351/9361 has an enhanced UART that is compatible with the
conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate
source. The P89LPC9331/9341/9351/9361 does include an independent baud rate
generator. The baud rate can be selected from the oscillator (divided by a constant),
Timer 1 overflow, or the independent baud rate generator. In addition to the baud rate
generation, enhancements over the standard 80C51 UART include Framing Error
detection, automatic address recognition, selectable double buffering and several
interrupt options. The UART can be operated in four modes: shift register, 8-bit UART,
9-bit UART, and CPU clock/32 or CPU clock/16.
7.23.1 Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at 116 of the CPU clock
frequency.
Fig 12. Capture/compare unit interrupts
002aaa896
interrupt to
CPU
TOIE2 (TICR2.7)
TOIF2 (TIFR2.7)
TICIE2A (TICR2.0)
TICF2A (TIFR2.0)
TICIE2B (TICR2.1)
TICF2B (TIFR2.1)
TOCIE2A (TICR2.3)
TOCF2A (TIFR2.3)
TOCIE2B (TICR2.4)
TOCF2B (TIFR2.4)
TOCIE2C (TICR2.5)
TOCF2C (TIFR2.5)
TOCIE2D (TICR2.6)
TOCF2D (TIFR2.6)
EA (IEN0.7)
ECCU (IEN1.4)
PRIORITY
ENCODER
other
interrupt
sources
ENCINT.0
ENCINT.1
ENCINT.2
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