參數(shù)資料
型號: P89LPC932A1FHN,151
廠商: NXP Semiconductors
文件頁數(shù): 18/64頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 28HVQFN
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 490
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LED,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 管件
配用: DB-TSSOP-LPC932-ND - BOARD FOR LPC932 TSSOP
622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
622-1003-ND - KIT FOR LCD DEMO
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱: 568-2250-5
935276347151
P89LPC932A1FHN-S
P89LPC932A1_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 12 March 2007
25 of 64
NXP Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
After power-up this input will function either as an external reset input or as a digital input
as dened by the RPE bit. Only a power-up reset will temporarily override the selection
dened by RPE bit. Other sources of reset will not override the RPE bit.
Reset can be triggered from the following sources:
External reset pin (during power-up or if user congured via UCFG1).
Power-on detect.
Brownout detect.
Watchdog timer.
Software reset.
UART break character detect reset.
For every reset source, there is a ag in the Reset Register, RSTSRC. The user can read
this register to determine the most recent reset source. These ag bits can be cleared in
software by writing a logic 0 to the corresponding bit. More than one ag bit may be set:
During a power-on reset, both POF and BOF are set but the other ag bits are
cleared.
For any other reset, previously set ag bits that have not been cleared will remain set.
7.16.1 Reset vector
Following reset, the P89LPC932A1 will fetch instructions from either address 0000H or
the Boot address. The Boot address is formed by using the Boot Vector as the high byte of
the address and the low byte of the address = 00H.
The Boot address will be used if a UART break reset occurs, or the non-volatile Boot
Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see
P89LPC932A1
User manual). Otherwise, instructions will be fetched from address 0000H.
7.17 Timers/counters 0 and 1
The P89LPC932A1 has two general purpose counter/timers which are upward compatible
with the standard 80C51 Timer 0 and Timer 1. Both can be congured to operate either as
timers or event counter. An option to automatically toggle the T0 and/or T1 pins upon timer
overow has been added.
In the ‘Timer’ function, the register is incremented every machine cycle.
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
once during every machine cycle.
Timer 0 and Timer 1 have ve operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1, 2
and 6 are the same for both Timers/Counters. Mode 3 is different.
7.17.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler. In this mode, the Timer register is congured as a
13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
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