參數(shù)資料
型號(hào): P89LPC932A1FHN,151
廠商: NXP Semiconductors
文件頁(yè)數(shù): 14/64頁(yè)
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 28HVQFN
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 490
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LED,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤(pán)
包裝: 管件
配用: DB-TSSOP-LPC932-ND - BOARD FOR LPC932 TSSOP
622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
622-1003-ND - KIT FOR LCD DEMO
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱(chēng): 568-2250-5
935276347151
P89LPC932A1FHN-S
P89LPC932A1_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 12 March 2007
21 of 64
NXP Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle
and a LOW in the next cycle, the interrupt request ag IEn in TCON is set, causing an
interrupt request.
If an external interrupt is enabled when the P89LPC932A1 is put into Power-down or Idle
mode, the interrupt will cause the processor to wake-up and resume operation. Refer to
7.13 I/O ports
The P89LPC932A1 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1 and 2
are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available depends
upon the clock and reset options chosen, as shown in Table 5.
Fig 8.
Interrupt sources, interrupt enables, and power-down wake-up sources
002aaa892
IE0
EX0
IE1
EX1
BOF
EBO
KBIF
EKBI
interrupt
to CPU
wake-up
(if in power-down)
EWDRT
CMF2
CMF1
EC
EA (IE0.7)
TF1
ET1
TI & RI/RI
ES/ESR
TI
EST
SI
EI2C
SPIF
ESPI
RTCF
ERTC
(RTCCON.1)
WDOVF
TF0
ET0
any CCU interrupt(1)
ECCU
EIEE
EEIF
Table 5.
Number of I/O pins available
Clock source
Reset option
Number of I/O pins
(28-pin package)
On-chip oscillator or watchdog oscillator
No external reset (except during power-up)
26
External RST pin supported
25
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