參數(shù)資料
型號(hào): P89LPC9321FN,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 21/71頁(yè)
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 28-DIP
產(chǎn)品培訓(xùn)模塊: LPC9351/9321 Overview
標(biāo)準(zhǔn)包裝: 13
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
EEPROM 大小: 512 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.600",15.24mm)
包裝: 管件
配用: 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
622-1003-ND - KIT FOR LCD DEMO
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱(chēng): 568-4700-5
935287657112
P89LPC9321FN
P89LPC9321
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 16 November 2010
28 of 71
NXP Semiconductors
P89LPC9321
8-bit microcontroller with accelerated two-clock 80C51 core
An open-drain port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
7.16.1.3
Input-only configuration
The input-only port configuration has no output drivers. It is a Schmitt trigger input that
also has a glitch suppression circuit.
7.16.1.4
Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous strong
pull-up when the port latch contains a logic 1. The push-pull mode may be used when
more source current is needed from a port output. A push-pull port pin has a
Schmitt triggered input that also has a glitch suppression circuit. The P89LPC9321 device
has high current source on eight pins in push-pull mode. See Table 9 “Limiting values”.
7.16.2 Port 0 analog functions
The P89LPC9321 incorporates two Analog Comparators. In order to give the best analog
function performance and to minimize power consumption, pins that are being used for
analog functions must have the digital outputs and digital inputs disabled.
Digital outputs are disabled by putting the port output into the Input-Only
(high-impedance) mode.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5.
On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions.
7.16.3 Additional port features
After power-up, all pins are in Input-Only mode. Please note that this is different from
the LPC76x series of devices.
After power-up, all I/O pins except P1.5, may be configured by software.
Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or
open-drain.
Every output on the P89LPC9321 has been designed to sink typical LED drive current.
However, there is a maximum total output current for all ports which must not be
exceeded. Please refer to Table 10 “Static characteristics” for detailed specifications.
All ports pins that can function as an output have slew rate controlled outputs to limit noise
generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
7.17 Power monitoring functions
The P89LPC9321 incorporates power monitoring functions designed to prevent incorrect
operation during initial power-up and power loss or reduction during operation. This is
accomplished with two hardware functions: Power-on detect and brownout detect.
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