參數(shù)資料
型號: P89LPC9221FDH,512
廠商: NXP Semiconductors
文件頁數(shù): 26/46頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 20-TSSOP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 75
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LED,POR,PWM,WDT
輸入/輸出數(shù): 18
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
包裝: 管件
配用: 622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1010-ND - BOARD FOR LPC922 TSSOP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-3223-5
935278674512
P89LPC9221FDH
Philips Semiconductors
P89LPC920/921/922/9221
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 08 — 15 December 2004
32 of 46
9397 750 14469
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.24 Flash program memory
8.24.1
General description
The P89LPC920/921/922/9221 Flash memory provides in-circuit electrical erasure
and programming. The Flash can be read, erased, or written as bytes. The Sector
and Page Erase functions can erase any Flash sector (1 kB) or page (64 bytes). The
Chip Erase operation will erase the entire program memory. In-System Programming
and standard parallel programming are both available. On-chip erase and write timing
generation contribute to a user-friendly programming interface. The
P89LPC920/921/922/9221 Flash reliably stores memory contents even after
10,000 erase and program cycles. The cell is designed to optimize the erase and
programming mechanisms. The P89LPC920/921/922/9221 uses VDD as the supply
voltage to perform the Program/Erase algorithms.
8.24.2
Features
Parallel programming with industry-standard commercial programmers.
In-Circuit serial Programming (ICP) with industry-standard commercial
programmers.
IAP-Lite allows individual and multiple bytes of code memory to be used for data
storage and programmed under control of the end application.
Internal xed boot ROM, containing low-level In-Application Programming (IAP)
routines that can be called from the end application (in addition to IAP-Lite).
Default serial loader providing In-System Programming (ISP) via the serial port,
located in upper end of user program memory.
Boot vector allows user-provided Flash loader code to reside anywhere in the
Flash memory space, providing exibility to the user.
Programming and erase over the full operating voltage range.
Read/Programming/Erase using ISP/IAP/IAP-Lite.
Any ash program or erase operation in 2 ms.
Programmable security for the code in the Flash for each sector.
>100,000 typical erase/program cycles for each byte.
10 year minimum data retention.
8.24.3
ISP and IAP capabilities of the P89LPC920/921/922/9221
Flash organization: The P89LPC920/921/922/9221 program memory consists of
two/four/eight 1 kB sectors. Each sector can be further divided into 64-byte pages. In
addition to sector erase, page erase, and byte erase, a 64-byte page register is
included which allows from 1 to 64 bytes of a given page to be programmed at the
same time, substantially reducing overall programming time. An In-Application
Programming (IAP) interface is provided to allow the end user’s application to erase
and reprogram the user code memory. In addition, erasing and reprogramming of
user-programmable bytes including UCFG1, the Boot Status Bit and the Boot Vector
are supported. As shipped from the factory, the upper 512 bytes of user code space
contains a serial In-System Programming (ISP) routine allowing for the device to be
programmed in circuit through the serial port.
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