參數(shù)資料
型號: P89LPC9151FDH,129
廠商: NXP Semiconductors
文件頁數(shù): 22/27頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 2KB 14TSSOP
標準包裝: 96
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 12
程序存儲器容量: 2KB(2K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b; D/A 1x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
包裝: 管件
其它名稱: 568-8738-5
935290259129
P89LPC9151FDH,129-ND
PIC18F87J72 FAMILY
DS39979A-page 86
Preliminary
2010 Microchip Technology Inc.
7.5.3
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.5.4
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
7.6
Flash Program Operation During
Code Protection
Protection” for details on code protection of Flash
program memory.
TABLE 7-2:
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
Page:
TBLPTRU
bit 21
Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT
Program Memory Table Latch
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
EECON2 EEPROM Control Register 2 (not a physical register)
EECON1
WPROG
FREE
WRERR
WREN
WR
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash program memory access.
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