參數(shù)資料
型號(hào): P89LPC913
廠商: NXP Semiconductors N.V.
英文描述: 8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM
中文描述: 8位微控制器兩個(gè)小時(shí)80C51的核心具有1KB 3伏閃光的128字節(jié)RAM
文件頁(yè)數(shù): 22/63頁(yè)
文件大?。?/td> 314K
代理商: P89LPC913
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P89LPC913 Special function registers
…continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
MSB
P
P
8
9
P
R
2
[1]
[2]
[3]
All ports are in input only (high impedance) state after power-up.
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any of them is written if BRGEN = 1, result is unpredictable.
The RSTSRC register reflects the cause of the P89LPC912 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is
xx110000.
After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after Watchdog reset and is ‘0’ after power-on reset. Other resets will
not affect WDTOF.
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
The only reset source that affects these SFRs is power-on reset.
[4]
[5]
[6]
WDL
WFEED1
WFEED2
Watchdog load
Watchdog feed 1
Watchdog feed 2
C1H
C2H
C3H
FF
11111111
Table 8:
Bit functions and addresses
Reset value
Hex
LSB
Binary
相關(guān)PDF資料
PDF描述
P89LPC914 8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM
P89LPC914FDH 8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM
P89LPC924 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converter
P89LPC925 8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converter
P89LPC930 8-bit microcontrollers with two-clock 80C51 core 4 kB/8 kB 3 V Flash with 256-byte data RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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