參數(shù)資料
型號: P89LPC9107
廠商: NXP Semiconductors N.V.
元件分類: 8位微控制器
英文描述: 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
中文描述: 8位微控制器兩個小時加速80C51的核心具有1KB 3伏字節(jié)可擦除閃存的8位A / D轉換器
文件頁數(shù): 50/58頁
文件大小: 257K
代理商: P89LPC9107
9397 750 14655
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 April 2005
50 of 58
Philips Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
[1]
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
Table 14:
V
DD
= 3.0 V to 3.6 V unless otherwise specified.
T
amb
=
40
°
C to +85
°
C for industrial applications, unless otherwise specified.
[1]
Symbol
Parameter
Dynamic characteristics (18 MHz)
Conditions
Variable clock
Min
7.189
f
ext
= 18 MHz
Min
7.189
Unit
Max
7.557
Max
7.557
f
OSC(RC)
internal RC oscillator frequency
(nominal f = 7.3728 MHz) trimmed
to
±
1 % at T
amb
= 25
°
C
internal RC oscillator frequency
(nominal f = 14.7456 MHz)
internal watchdog oscillator
frequency (nominal f = 400 kHz)
clock cycle time
low power select clock frequency
External clock
f
ext
external clock frequency
t
CHCX
HIGH time
t
CLCX
LOW time
t
CLCH
rise time
t
CHCL
fall time
Glitch filter
t
gr
glitch rejection
clock doubler
option = OFF
(default)
clock doubler
option = ON
MHz
14.378
15.114
14.378
15.114
MHz
f
OSC(WD)
320
520
320
520
kHz
T
cy(CLK)
f
CLKLP
see
Figure 19
83
0
-
8
-
-
-
-
ns
MHz
-
-
0
22
22
-
-
18
-
-
5
5
MHz
ns
ns
ns
ns
see
Figure 19
22
22
-
-
T
cy(CLK)
t
CLCX
T
cy(CLK)
t
CHCX
5
5
P1.5/RST pin
any pin except
P1.5/RST
P1.5/RST pin
any pin except
P1.5/RST
-
-
50
15
-
-
50
15
ns
ns
t
sa
signal acceptance
125
50
-
-
125
50
-
-
ns
ns
Shift register (UART mode 0 - P89LPC9103)
t
XLXL
serial port clock cycle time
t
QVXH
output data set-up to clock rising
edge
t
XHQX
output data hold after clock rising
edge
t
XHDX
input data hold after clock rising
edge
t
XHDV
input data valid to clock rising edge see
Figure 18
see
Figure 18
see
Figure 18
16T
cy(CLK)
13T
cy(CLK)
-
-
888
722
-
-
ns
ns
see
Figure 18
-
T
cy(CLK)
+ 20
-
75
ns
see
Figure 18
-
0
-
0
ns
150
-
150
-
ns
相關PDF資料
PDF描述
P89LPC9107FDH 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
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