參數(shù)資料
型號(hào): P89LPC9107
廠商: NXP Semiconductors N.V.
元件分類: 8位微控制器
英文描述: 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
中文描述: 8位微控制器兩個(gè)小時(shí)加速80C51的核心具有1KB 3伏字節(jié)可擦除閃存的8位A / D轉(zhuǎn)換器
文件頁(yè)數(shù): 37/58頁(yè)
文件大?。?/td> 257K
代理商: P89LPC9107
9397 750 14655
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 April 2005
37 of 58
Philips Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
8.18.9
Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated
when the double buffer is ready to receive new data.
8.18.10
The 9
th
bit (bit 8) in double buffering (Modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as long
as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until
the bit is shifted out, as indicated by the Tx interrupt.
If double buffering is enabled, TB8
must
be updated before SBUF is written, as TB8 will
be double-buffered together with SBUF data.
8.19 Analog comparators
One analog comparator is provided on the P89LPC9102/9103/9107. Comparator
operation is such that the output is a logic 1 (which may be read in a register) when the
positive input is greater than the negative input (selectable from a pin or an internal
reference voltage). Otherwise the output is a zero. The comparator may be configured to
cause an interrupt when the output value changes.
The connections to the comparator are shown in
Figure 15
. The comparator functions to
V
DD
= 2.4 V.
When the comparator is first enabled, the comparator’s interrupt flag is not guaranteed to
be stable for 10 microseconds. The comparator interrupt should not be enabled during
that time, and the comparator interrupt flag must be cleared before the interrupt is enabled
in order to prevent an immediate interrupt service.
When a comparator is disabled the comparator’s output, COx, goes HIGH. If the
comparator output was LOW and then is disabled, the resulting transition of the
comparator output from a LOW to HIGH state will set the comparator flag, CMFx. This will
cause an interrupt if the comparator interrupt is enabled. The user should therefore
disable the comparator interrupt prior to disabling the comparator. Additionally, the user
should clear the comparator flag, CMFx, after disabling the comparator.
8.20 Internal reference voltage
An internal reference voltage generator may supply a default reference when a single
comparator input pin is used. The value of the internal reference voltage, referred to as
V
REF
, is 1.23 V
±
10 %.
Fig 15. Comparator input and output connections.
comparator
CN1
(P0.4) CIN1A
(P0.3) CIN1B
(P0.5) CMPREF
V
REF
CO1
002aaa979
change detect
CMF1
interrupt
EC
CP1
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P89LPC9107FDH 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
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