參數(shù)資料
型號: P89LPC908FD
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM
中文描述: 8-BIT, FLASH, 7.3728 MHz, MICROCONTROLLER, PDSO8
封裝: 3.90 MM, PLASTIC, MS-012, SOT-96-1, SO-8
文件頁數(shù): 45/51頁
文件大?。?/td> 243K
代理商: P89LPC908FD
Philips Semiconductors
P89LPC906/907/908
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 05 — 17 December 2004
45 of 51
9397 750 14467
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11. Dynamic characteristics
[1]
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
Table 14:
V
DD
= 2.4 V to 3.6 V unless otherwise specified.
T
amb
=
40
°
C to +85
°
C for industrial, unless otherwise specified.
[1]
Symbol
Parameter
AC characteristics
Conditions
Variable clock
Min
7.189
f
osc
= 12 MHz
Min
7.189
Unit
Max
7.557
Max
7.557
f
RCOSC
internal RC oscillator frequency
(nominal f = 7.3728 MHz) trimmed
to
±
1 % at T
amb
= 25
°
C
internal Watchdog oscillator
frequency (nominal f = 400 kHz)
Crystal oscillator (P89LPC906)
f
osc
oscillator frequency
t
CLCL
clock cycle
f
CLKP
CLKLP active frequency
Glitch filter
glitch rejection, P1.5/RST pin
signal acceptance, P1.5/RST pin
glitch rejection, any pin except
P1.5/RST
signal acceptance, any pin except
P1.5/RST
External clock (P89LPC906)
t
CHCX
HIGH time
t
CLCX
LOW time
t
CLCH
rise time
t
CHCL
fall time
Shift register (UART mode 0 - P89LPC908)
t
XLXL
serial port clock cycle time
t
QVXH
output data set-up to clock rising
edge
t
XHQX
output data hold after clock rising
edge
t
XHDX
input data hold after clock rising
edge
t
DVXH
input data valid to clock rising edge see
Figure 18
MHz
f
WDOSC
320
520
320
520
kHz
0
83
0
12
-
8
-
-
-
-
-
-
MHz
ns
MHz
see
Figure 19
-
125
-
50
-
15
-
125
-
50
-
15
ns
ns
ns
50
-
50
-
ns
see
Figure 19
see
Figure 19
see
Figure 19
see
Figure 19
33
33
-
-
t
CLCL
t
CLCX
t
CLCL
t
CHCX
8
8
33
33
-
-
-
-
8
8
ns
ns
ns
ns
see
Figure 18
see
Figure 18
16 t
CLCL
13 t
CLCL
-
-
1333
1083
-
-
ns
ns
see
Figure 18
-
t
CLCL
+ 20
-
103
ns
see
Figure 18
-
0
-
0
ns
150
-
150
-
ns
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