參數(shù)資料
型號: P89LPC908FD
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM
中文描述: 8-BIT, FLASH, 7.3728 MHz, MICROCONTROLLER, PDSO8
封裝: 3.90 MM, PLASTIC, MS-012, SOT-96-1, SO-8
文件頁數(shù): 25/51頁
文件大小: 243K
代理商: P89LPC908FD
Philips Semiconductors
P89LPC906/907/908
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 05 — 17 December 2004
25 of 51
9397 750 14467
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
external circuit is required to hold the device in reset at power-up until V
DD
has
reached its specified level. When system power is removed V
DD
will fall below
the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when V
DD
falls below the minimum
specified operating voltage.
If CCLK is 8 MHz or slower, the CLKLP SFR bit
(AUXR1.7) can be set to ‘1’ to reduce power consumption. On reset, CLKLP is ‘0’
allowing highest performance access. This bit can then be set in software if CCLK is
running at 8 MHz or slower.
8.2.6
Clock output (P89LPC906)
The P89LPC906 supports a user selectable clock output function on the
XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if
another clock source has been selected (on-chip RC oscillator, Watchdog oscillator,
external clock input on X1) and if the Real-Time clock is not using the crystal
oscillator as its clock source. This allows external devices to synchronize to the
P89LPC906. This output is enabled by the ENCLK bit in the TRIM register. The
frequency of this clock output is
1
2
that of the CCLK. If the clock output is not needed
in Idle mode, it may be turned off prior to entering Idle, saving additional power.
8.3 On-chip RC oscillator option
The P89LPC906/907/908 has a 6-bit TRIM register that can be used to tune the
frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory
pre-programmed value to adjust the oscillator frequency to 7.373 MHz,
±
2.5 %.
End-user applications can write to the Trim register to adjust the on-chip RC oscillator
to other frequencies. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can
be set to ‘1’ to reduce power consumption. On reset, CLKLP is ‘0’ allowing highest
performance access. This bit can then be set in software if CCLK is running at 8 MHz
or slower.
8.4 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz. This
oscillator can be used to save power when a high clock frequency is not needed.
8.5 External clock input option (P89LPC906)
In this configuration, the processor clock is derived from an external source driving
the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2/P3.0 pin
may be used as a standard port pin or a clock output.
When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until V
DD
has
reached its specified level. When system power is removed V
DD
will fall below
the minimum specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when V
DD
falls below the minimum
specified operating voltage.
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