參數(shù)資料
型號(hào): P89LPC904
廠(chǎng)商: NXP Semiconductors N.V.
元件分類(lèi): 8位微控制器
英文描述: 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
中文描述: 8位微控制器兩個(gè)小時(shí)加速80C51的核心具有1KB 3伏字節(jié)可擦除閃存的8位A / D轉(zhuǎn)換器
文件頁(yè)數(shù): 36/41頁(yè)
文件大?。?/td> 190K
代理商: P89LPC904
Philips Semiconductors
P89LPC904
8-bit microcontrollers with two-clock accelerated 80C51 core
Preliminary data
Rev. 02 — 25 June 2004
36 of 41
9397 750 13521
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11. Dynamic characteristics
[1]
[2]
Parameters are valid over operating temperature range unless otherwise specified.
Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
Table 9:
T
amb
=
40
°
C to +85
°
C for industrial, unless otherwise specified.
[1]
Symbol
Parameter
AC characteristics
Conditions
Variable clock
Min
7.189
f
ext
= 12 MHz
Min
7.189
Unit
Max
7.557
Max
7.557
f
RCOSC
internal RC oscillator frequency
(nominal f = 7.3728 MHz) trimmed
to
±
1 % at T
amb
= 25
°
C
internal Watchdog oscillator
frequency (nominal f = 400 kHz)
MHz
f
WDOSC
280
480
280
480
kHz
Glitch filter
glitch rejection, P1.5/RST pin
signal acceptance, P1.5/RST pin
glitch rejection, any pin except
P1.5/RST
signal acceptance, any pin except
P1.5/RST
Shift register (UART mode 0)
t
XLXL
serial port clock cycle time
t
QVXH
output data set-up to clock rising
edge
t
XHQX
output data hold after clock rising
edge
t
XHDX
input data hold after clock rising
edge
t
DVXH
input data valid to clock rising edge see
Figure 10
-
125
-
50
-
15
-
125
-
50
-
15
ns
ns
ns
50
-
50
-
ns
see
Figure 10
see
Figure 10
16t
CLCL
13t
CLCL
-
-
1333
1083
-
-
ns
ns
see
Figure 10
-
t
CLCL
+ 20
-
103
ns
see
Figure 10
-
0
-
0
ns
150
-
150
-
ns
Fig 10. Shift register mode timing.
0
1
2
3
4
5
6
7
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
tXLXL
002aaa425
Set TI
Set RI
tXHQX
tQVXH
tXHDV
tXHDX
Clock
Output Data
Write to SBUF
Input Data
Clear RI
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