參數(shù)資料
型號: P89LPC904
廠商: NXP Semiconductors N.V.
元件分類: 8位微控制器
英文描述: 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
中文描述: 8位微控制器兩個小時加速80C51的核心具有1KB 3伏字節(jié)可擦除閃存的8位A / D轉(zhuǎn)換器
文件頁數(shù): 26/41頁
文件大?。?/td> 190K
代理商: P89LPC904
Philips Semiconductors
P89LPC904
8-bit microcontrollers with two-clock accelerated 80C51 core
Preliminary data
Rev. 02 — 25 June 2004
26 of 41
9397 750 13521
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
reaches all logic 0s, the counter will be reloaded again and the RTCF flag will be set.
The clock source for this counter is the CPU clock (CCLK). Only power-on reset will
reset the Real-Time clock and its associated SFRs to the default state.
8.19 UART
The P89LPC904 has an enhanced UART that is compatible with the conventional
80C51 UART except that Timer 2 overflow cannot be used as a baud rate source.
The P89LPC904 does include an independent Baud Rate Generator. The baud rate
can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the
independent Baud Rate Generator. In addition to the baud rate generation,
enhancements over the standard 80C51 UART include Framing Error detection,
automatic address recognition, selectable double buffering and several interrupt
options. The UART can be operated in 4 modes: shift register, 8-bit UART, 9-bit
UART, and CPU clock/32 or CPU clock/16.
8.19.1
Mode 0
Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at
1
16
of the CPU clock
frequency.
8.19.2
Mode 1
10 bits are transmitted (through TxD) or received (through RxD): a start bit (logic 0),
8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is
stored in RB8 in Special Function Register SCON. The baud rate is variable and is
determined by the Timer 1 overflow rate or the Baud Rate Generator (described in
Section 8.19.5 “Baud rate generator and selection”
).
8.19.3
Mode 2
11 bits are transmitted (through TxD) or received (through RxD): start bit (logic 0),
8 data bits (LSB first), a programmable 9
th
data bit, and a stop bit (logic 1). When
data is transmitted, the 9
th
data bit (TB8 in SCON) can be assigned the value of
logic 0 or logic 1. Or, for example, the parity bit (P, in the PSW) could be moved into
TB8. When data is received, the 9
th
data bit goes into RB8 in Special Function
Register SCON, while the stop bit is not saved. The baud rate is programmable to
either
1
16
or
1
32
of the CPU clock frequency, as determined by the SMOD1 bit in
PCON.
8.19.4
Mode 3
11 bits are transmitted (through TxD) or received (through RxD): a start bit (logic 0), 8
data bits (LSB first), a programmable 9
th
data bit, and a stop bit (logic 1). In fact,
Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in
Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate
Generator (described in
Section 8.19.5 “Baud rate generator and selection”
).
8.19.5
Baud rate generator and selection
The P89LPC904 enhanced UART has an independent Baud Rate Generator. The
baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0
SFRs which together form a 16-bit baud rate divisor value that works in a similar
manner as Timer 1. If the baud rate generator is used, Timer 1 can be used for other
timing functions.
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