參數(shù)資料
型號(hào)： P89C738ABP
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-bit Flash microcontrollers
中文描述： 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PDIP40
封裝： 0.600 INCH, PLASTIC, SOT-129-1, DIP-40
文件頁(yè)數(shù)： 35/64頁(yè)
文件大?。?/td> 360K
代理商： P89C738ABP
1998 Apr 07
35
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
16.5
Silicon-ID-Read command
MTP memories are intended for use in applications where
the local CPU alters memory contents. As such,
manufacturer and device-codes must be accessible while
the device resides in the target system.
P89C738 contains a Silicon-ID-Read operation.
The operation is initiated by writing 90H into the command
register. Following the command write, a read cycle from
address 0000H retrieves the manufacturer code: C2H.
A read cycle from address 0001H returns the device
code: 1AH.
16.6
Set-up of Automatic chip erase and Automatic
erase commands
The Automatic chip erase does not require the device to be
entirely pre-programmed prior to executing the set-up of
Automatic erase command and Automatic chip erase
commands. Upon executing the Automatic chip erase
command, the device automatically will program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The erase
and verify operations are complete when the data on DQ7
is a logic 1 at which time the device returns to the standby
mode. The system is not required to provide any control or
timing during these operations.
When using the Automatic chip erase algorithm, note that
the erase automatically terminates when adequate erase
margin has been achieved for the memory array (no erase
verify command is required). The margin voltages are
internally generated in the same manner as when the
standard erase verify command is used.
The set-up of the Automatic erase command is a
command only operation that stages the device for
automatic electrical erasure of all bytes in the array.
The set-up Automatic erase is performed by writing 30H to
the command register.
To execute the Automatic chip erase, 30H must be written
again to the command register. The automatic chip erase
begins on the rising edge of the WE and terminates when
the data on DQ7 is a logic 1 and the data on DQ6 stops
toggling for two consecutive read cycles, at which time the
device returns to the standby mode.
16.7
Set-up of the Automatic program and Program
commands
The set-up of the Automatic program is a command only
operation that stages the devices for automatic
programming.
The set-up of Automatic program is performed by writing
40H to the command register.
Once the set-up of the Automatic program operation is
performed, the next WE pulse causes a transition to an
active programming operation. Addresses are internally
latched on the falling edge of the WE pulse. Data is
internally latched on the rising edge of the WE pulse.
The rising edge of WE also starts the programming
operation. The system is not required to provide further
controls or timings. The device will automatically provide
an adequate internally generated program pulse and verify
margin. The automatic programming operation is
completed when the data read on DQ6 stops toggling for
two consecutive read cycles and the data on DQ7 and
DQ6 are equivalent to data written to these two bits at
which time the device returns to the read mode (no
program verify command is required; but data can be read
out if OE is active LOW).
16.8
Reset command
A reset command is provided as a means to safely abort
the erase or program command sequences.
Following either set-up command (erase or program) with
two consecutive writes of FFH will safely abort the
operation. Memory contents will not be altered. Should
program-fail or erase-fail happen, two consecutive writes
of FFH will reset the device to abort the operation. A valid
command must then be written to place the device in the
desired state.
16.9
Write operation status
16.9.1
Toggle bit DQ6
The P89C738 features a ‘toggle bit’ as a method to
indicate to the host system that the Automatic program or
erase algorithms are either in progress or completed.
While the Automatic program or erase algorithm is in
progress, successive attempts to read data from the
device will result in DQ6 toggling between a logic 1and a
logic 0. Once the Automatic program or erase algorithm is
completed, DQ6 will stop toggling and valid data will be
read. The toggle bit is valid after the rising edge of the
second WE pulse of the two write pulse sequences.
Toggle bit appears in Q6, when program or erase is
operating.
相關(guān)PDF資料
PDF描述
P89C739 8-bit Flash microcontrollers
P89LPC904 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
P89LPC904FD 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
P89LPC9102 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
P89LPC9107 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
P89C738BBB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
P89C739 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit Flash microcontrollers
P89C739ABA 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit Flash microcontrollers
P89C739ABB 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit Flash microcontrollers
P89CE528EBA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*