參數(shù)資料
型號(hào)： P89C557E6
廠(chǎng)商： NXP Semiconductors N.V.
英文描述： Single-chip 8-bit microcontroller(單片8位微控制器)
中文描述： 單芯片8位微控制器（單片8位微控制器）
文件頁(yè)數(shù)： 56/64頁(yè)
文件大小： 476K
代理商： P89C557E6
Philips Semiconductors
Product specification
P83C557E6/P80C557E6
Single-chip 8-bit microcontroller
1999 Mar 02
56
11.
AC CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
V
DD
= 5 V
±
10% (EBx), V
SS
= 0 V, t
CLK
min = 1/fmax (maximum operating frequency)
V
DD
= 5 V
±
10% (EFx), V
SS
= 0 V, t
CLK
min = 1/fmax (maximum operating frequency)
T
amb
= 0
°
C to +70
°
C, t
CLK
min = 63 ns for P8xC557E6EBx
T
amb
= –40
°
C to +85
°
C, t
CLK
min = 63 ns for P8xC557E6EFx
C1 = 100 pF for Port 0, ALE and PSEN ; C1 = 80 pF for all other outputs unless otherwise specified.
12MHz CLOCK
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
1/t
CLK
t
LHLL
53
System clock frequency
3.5
16
MHz
53
ALE pulse width
127
85
2t
CLK
–40
ns
t
AVLL
t
LLAX
t
LLIV
t
LLPL
53
Address valid to ALE LOW
43
23
t
CLK
–40
t
CLK
–30
ns
53
Address hold after ALE LOW
53
33
ns
53
ALE LOW to valid instruction in
234
150
4t
CLK
–100
ns
53
ALE LOW to PSEN LOW
53
33
t
CLK
–30
ns
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
53
PSEN pulse width
205
143
3t
CLK
–45
ns
53
PSEN LOW to valid instruction in
145
83
3t
CLK
–105
ns
53
Input instruction hold after PSEN
0
0
0
ns
53
Input instruction float after PSEN
59
38
t
CLK
–25
5t
CLK
–105
ns
53
Address to valid instruction in
312
208
ns
t
PLAZ
53
PSEN LOW to address float
10
10
10
ns
Data Memory
t
AVLL
t
LLAX
54, 55
Address valid to ALE LOW
43
23
t
CLK
–40
t
CLK
–35
ns
54, 55
Address hold after ALE LOW
48
28
ns
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
54
RD pulse width
400
275
6t
CLK
–100
6t
CLK
–100
ns
55
WR pulse width
400
275
ns
54
RD LOW to valid data in
252
148
5t
CLK
–165
ns
54
Data hold after RD
0
0
0
ns
54
Data float after RD
97
55
2t
CLK
–70
ns
t
LLDV
t
AVDV
t
LLWL
t
AVWL
54
ALE LOW to valid data in
517
350
8t
CLK
–150
9t
CLK
–165
3t
CLK
+50
ns
54
Address to valid data in
585
398
ns
54, 55
ALE LOW to RD or WR LOW
200
300
138
238
3t
CLK
–50
4t
CLK
–130
ns
54, 55
Address valid to WR LOW or RD LOW
203
120
ns
t
QVWX
t
QVWH
t
WHQX
t
RLAZ
t
WHLH
UART Timing – Shift Register Mode
(Test Conditions: T
amb
= 0
°
C to +70
°
C; V
SS
= 0 V; Load Capacitance = 80pF)
t
XLXL
57
Serial port clock cycle time
t
QVXH
57
Output data setup to clock rising edge
t
XHQX
57
Output data hold after clock rising edge
55
Data valid to WR transition
33
13
t
CLK
–50
7t
CLK
–150
t
CLK
–50
ns
55
Data before WR
433
288
ns
55
Data hold after WR
33
13
ns
54
RD low to address float
0
0
0
ns
54, 55
RD or WR HIGH to ALE HIGH
43
123
23
103
t
CLK
–40
t
CLK
+40
ns
1.0
0.75
12t
CLK
10t
CLK
–133
2t
CLK
–117
μ
s
700
492
ns
50
8
ns
t
XHDX
t
XHDV
57
Input data hold after clock rising edge
0
0
0
ns
57
Clock rising edge to input data valid
700
492
10t
CLK
–133
ns
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