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參數(shù)資料
| 型號： | P89C557E6 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Single-chip 8-bit microcontroller(單片8位微控制器) |
| 中文描述： | 單芯片8位微控制器（單片8位微控制器） |
| 文件頁數(shù)： | 45/64頁 |
| 文件大?。?/td> | 476K |
| 代理商： | P89C557E6 |
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Philips Semiconductors
Product specification
P83C557E6/P80C557E6
Single-chip 8-bit microcontroller
1999 Mar 02
45
6.14
The reset input pin RSTIN is connected to a Schmitt trigger for noise
reduction (see Figure 46). Is the HF–oscillator selected a Reset is
accomplished by holding the RSTIN pin HIGH for at least 2 machine
cycles (24 system clock periods). Is the PLL–oscillator selected the
RSTIN–pulse must have a width of 1
μ
s at least, independent of the
32 kHz–oscillator is running or not (see PLL description). The CPU
responds by executing an internal reset. The RSTOUT pin
represents the signal resetting the CPU and can be used to reset
peripheral devices.
Reset Circuitry
The RSTOUT level also could be high due to a Watchdog timer
overflow.
The length of the output pulse from T3 is 3 machine cycles. A pulse
of such short duration is necessary in order to recover from a
processor or system fault as fast as possible.
During Reset, ALE and PSEN output a HIGH level. In order to
perform a correct reset, this level must not be affected by external
elements.
A Reset leaves the internal registers as shown in Table 5.
The internal RAM is not affected by Reset. At power-on, the RAM
content is indeterminate.
6.15
An automatic Reset can be obtained by switching on V
DD
, if the
RSTIN pin is connected to V
DD
via a capacitor, as shown in
Figure 47.
Power-on Reset
If the HF oscillator selected the V
DD
rise time must not exceed 10
ms and the capacitor should be at least 2.2
μ
F. The decrease of the
RSTIN pin voltage depends on the capacitor and the internal resistor
R
RST
. That voltage must remain above the lower threshold for at
minimum the HF–oscillator start–up time plus 2 machine cycles.
Is the PLL–oscillator selected a 0.1
μ
F capacitor is sufficient to
obtain an automatic reset.
8xC557E6
V
DD
RST
R
RST
HF_osc.: 2.2
F
PLL_osc.: 0.1 F
V
DD
Figure 46. On–chip Reset Configuration
R
RST
RSTIN
Schmitt
Trigger
On-chip
resistor
Overflow
timer T3
Figure 47. Power–on Reset
MUX
RSTOUT
Internal
Reset
SELXTAL1
PLL
OSC
Capacitor for
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