參數(shù)資料
型號: P89C51UFPN
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: DRILL BIT SET, TIN 19 PIECEDRILL BIT SET, TIN 19 PIECE; Material:Titanium
中文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PDIP40
封裝: 0.600 INCH, PLASTIC, MO-015AJ, SOT-129-1, DIP-40
文件頁數(shù): 7/68頁
文件大?。?/td> 404K
代理商: P89C51UFPN
Philips Semiconductors
Preliminary data
P89C51RA2/RB2/RC2/RD2xx
80C51 8-bit Flash microcontroller family
8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM
2002 Jul 18
7
PIN DESCRIPTIONS
MNEMONIC
PIN NUMBER
TYPE
NAME AND FUNCTION
PDIP
PLCC
LQFP
V
SS
V
CC
20
22
16
I
Ground:
0 V reference.
40
44
38
I
Power Supply:
This is the power supply voltage for normal, idle, and power-down
operation.
P0.0–0.7
39–32
43–36
37–30
I/O
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high-impedance inputs. Port 0 is also the
multiplexed low-order address and data bus during accesses to external program
and data memory. In this application, it uses strong internal pull-ups when emitting 1s.
P1.0–P1.7
1–8
2–9
40–44,
1–3
I/O
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins.
Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 1 pins that are externally pulled low will
source current because of the internal pull-ups. (See DC Electrical Characteristics:
I
IL
).
Alternate functions for P89C51RA2/RB2/RC2/RD2xx Port 1 include:
T2 (P1.0):
Timer/Counter 2 external count input/Clockout (see Programmable
Clock-Out)
T2EX (P1.1):
Timer/Counter 2 Reload/Capture/Direction Control
ECI (P1.2):
External Clock Input to the PCA
CEX0 (P1.3):
Capture/Compare External I/O for PCA module 0
CEX1 (P1.4):
Capture/Compare External I/O for PCA module 1
CEX2 (P1.5):
Capture/Compare External I/O for PCA module 2
CEX3 (P1.6):
Capture/Compare External I/O for PCA module 3
CEX4 (P1.7):
Capture/Compare External I/O for PCA module 4
1
2
40
I/O
2
3
4
5
6
7
8
3
4
5
6
7
8
9
41
42
43
44
1
2
3
I
I
I/O
I/O
I/O
I/O
I/O
P2.0–P2.7
21–28
24–31
18–25
I/O
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 2 pins that are externally being pulled low will source current
because of the internal pull-ups. (See DC Electrical Characteristics: I
IL
). Port 2
emits the high-order address byte during fetches from external program memory
and during accesses to external data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s.
During accesses to external data memory that use 8-bit addresses (MOV @Ri),
port 2 emits the contents of the P2 special function register.
P3.0–P3.7
10–17
11,
13–19
5, 7–13
I/O
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 3 pins that are externally being pulled low will source current
because of the pull-ups. (See DC Electrical Characteristics: I
IL
). Port 3 also serves
the special features of the P89C51RA2/RB2/RC2/RD2xx, as listed below:
RxD (P3.0):
Serial input port
TxD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt
INT1 (P3.3):
External interrupt
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
I
O
I
I
I
I
O
O
RST
9
10
4
I
Reset:
A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal resistor to V
SS
permits a power-on reset using only
an external capacitor to V
CC
.
Address Latch Enable:
Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted twice
every machine cycle, and can be used for external timing or clocking. Note that one
ALE pulse is skipped during each access to external data memory. ALE can be
disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a
MOVX instruction.
ALE
30
33
27
O
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