參數(shù)資料
型號： P89C51UFPN
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： DRILL BIT SET, TIN 19 PIECEDRILL BIT SET, TIN 19 PIECE; Material:Titanium
中文描述： 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PDIP40
封裝： 0.600 INCH, PLASTIC, MO-015AJ, SOT-129-1, DIP-40
文件頁數(shù)： 57/68頁
文件大小： 404K
代理商： P89C51UFPN
Philips Semiconductors
Preliminary data
P89C51RA2/RB2/RC2/RD2xx
80C51 8-bit Flash microcontroller family
8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM
2002 Jul 18
57
AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE)
T
amb
= 0
°
C to +70
°
C or –40
°
C to +85
°
C; V
CC
= 5 V
±
10%, V
SS
= 0 V
1, 2, 3
VARIABLE CLOCK
4
MIN
0
2t
CLCL
–40
t
CLCL
–25
t
CLCL
–25
33 MHz CLOCK
4
MIN
SYMBOL
1/t
CLCL
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
WHQX
t
QVWH
t
RLAZ
t
WHLH
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Shift Register
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to
Port 0 drivers.
4. Parts are tested to 3.5 MHz, but guaranteed to operate down to 0 Hz.
FIGURE
42
42
42
42
42
42
42
42
42
42
42
42
PARAMETER
MAX
33
MAX
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
21
5
5
4t
CLCL
–65
55
t
CLCL
–25
3t
CLCL
–45
5
45
3t
CLCL
–60
30
0
0
t
CLCL
–25
5t
CLCL
–80
10
5
70
10
43, 44
43, 44
43, 44
43, 44
43, 44
43, 44
43, 44
43, 44
43, 44
43, 44
43, 44
44
43, 44
43, 44
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
6t
CLCL
–100
6t
CLCL
–100
82
82
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5t
CLCL
–90
60
0
0
2t
CLCL
–28
8t
CLCL
–150
9t
CLCL
–165
3t
CLCL
+50
32
90
105
140
3t
CLCL
–50
4t
CLCL
–75
t
CLCL
–30
t
CLCL
–25
7t
CLCL
–130
40
45
0
5
80
0
0
55
t
CLCL
–25
t
CLCL
+25
5
46
46
46
46
High time
Low time
Rise time
Fall time
17
17
t
CLCL
–t
CLCX
t
CLCL
–t
CHCX
5
5
ns
ns
ns
ns
45
45
45
45
45
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
12t
CLCL
10t
CLCL
–133
2t
CLCL
–80
0
360
167
50
0
ns
ns
ns
ns
ns
10t
CLCL
–133
167
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