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參數(shù)資料
| 型號： | P89C51RC2 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 80C51 8-bit Flash microcontroller family |
| 中文描述： | 80C51的8位閃存微控制器系列 |
| 文件頁數(shù)： | 11/68頁 |
| 文件大?。?/td> | 404K |
| 代理商： | P89C51RC2 |
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Philips Semiconductors
Preliminary data
P89C51RA2/RB2/RC2/RD2xx
80C51 8-bit Flash microcontroller family
8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM
2002 Jul 18
11
CLOCK CONTROL REGISTER (CKCON)
This device provides control of the 6-clock/12-clock mode by means
of both an SFR bit (X2) and a Flash bit (FX2, located in the Security
Block). The Flash clock control bit, FX2, when programmed (6-clock
mode) supercedes the X2 bit (CKCON.0).
The CKCON register also provides individual control of the clock
rates for the peripherals devices. When running in 6-clock mode
each peripheral may be individually clocked from either fosc/6 or
fosc/12. When in 12-clock mode, all peripheral devices will use
fosc/12. The CKCON register is shown below.
X2
BIT
CKCON.7
CKCON.6
CKCON.5
CKCON.4
CKCON.3
CKCON.2
CKCON.1
CKCON.0
SYMBOL
–
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
FUNCTION
Reserved.
Watchdog clock; 0 = 6 clocks for each WDT clock, 1 = 12 clocks for each WDT clock
PCA clock; 0 = 6 clocks for each PCA clock, 1 = 12 clocks for each PCA clock
UART clock; 0 = 6 clocks for each UART clock, 1 = 12 clocks for each UART clock
Timer2 clock; 0 = 6 clocks for each Timer2 clock, 1 = 12 clocks for each Timer2 clock
Timer1 clock; 0 = 6 clocks for each Timer1 clock, 1 = 12 clocks for each Timer1 clock
Timer0 clock; 0 = 6 clocks for each Timer0 clock, 1 = 12 clocks for each Timer0 clock
CPU clock; 1 = 6 clocks for each machine cycle, 0 = 12 clocks for each machine cycle
SU01607
T0X2
T1X2
T2X2
SIX2
PCAX2
WDX2
–
Not Bit Addressable
CKCON
Address = 8Fh
Reset Value =
x0000000B
7
6
5
4
3
2
1
0
Bits 1 through 6 only apply if 6 clocks per machine cycle is chosen
(i.e.– Bit 0 = 1). If Bit 0 = 0 (12 clocks per machine cycle) then all
peripherals will have 12 clocks per machine cycle as their clock
source.
Also please note that the clock divider applies to the serial port for
modes 0 & 2 (fixed baud rate modes). This is because modes 1 & 3
(variable baud rate modes) use either Timer 1 or Timer 2.
Below is the truth table for the peripheral input clock sources.
FX2 clock mode bit
X2
Peripheral clock
mode bit
(e.g., T0X2)
x
0
1
0
1
CPU MODE
Peripheral Clock Rate
erased
erased
erased
programmed
programmed
0
1
1
x
x
12-clock (default)
6-clock
6-clock
6-clock
6-clock
12-clock (default)
6-clock
12-clock
6-clock
12-clock
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (12 oscillator periods in 6-clock mode, or 24 oscillator
periods in 12-clock mode), while the oscillator is running. To ensure a
good power-on reset, the RST pin must be high long enough to allow
the oscillator time to start up (normally a few milliseconds) plus two
machine cycles. At power-on, the voltage on V
CC
and RST must
come up at the same time for a proper start-up. Ports 1, 2, and 3 will
asynchronously be driven to their reset condition when a voltage
above V
IH1
(min.) is applied to RST.
The value on the EA pin is latched when RST is deasserted and has
no further effect.
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