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參數(shù)資料
| 型號(hào)： | P87LPC767FN,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 11/61頁 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU 4K OTP 20-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 系列： | LPC700 |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | I²C，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，LED，POR，WDT |
| 輸入/輸出數(shù)： | 18 |
| 程序存儲(chǔ)器容量： | 4KB（4K x 8） |
| 程序存儲(chǔ)器類型： | OTP |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 其它名稱： | 568-3217-5 935267192112 P87LPC767FN |
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Philips Semiconductors
Product data
P87LPC767
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
2002 Mar 25
16
BIT
SYMBOL
FUNCTION
I2CON.7
RDAT
Read: the most recently received data bit.
“
CXA
Write: clears the transmit active flag.
I2CON.6
ATN
Read: ATN = 1 if any of the flags DRDY, ARL, STR, or STP = 1.
“
IDLE
Write: in the I2C slave mode, writing a 1 to this bit causes the I2C hardware to ignore the bus until it
is needed again.
I2CON.5
DRDY
Read: Data Ready flag, set when there is a rising edge on SCL.
“
CDR
Write: writing a 1 to this bit clears the DRDY flag.
I2CON.4
ARL
Read: Arbitration Loss flag, set when arbitration is lost while in the transmit mode.
“
CARL
Write: writing a 1 to this bit clears the CARL flag.
I2CON.3
STR
Read: Start flag, set when a start condition is detected at a master or non-idle slave.
“
CSTR
Write: writing a 1 to this bit clears the STR flag.
I2CON.2
STP
Read: Stop flag, set when a stop condition is detected at a master or non-idle slave.
“
CSTP
Write: writing a 1 to this bit clears the STP flag.
I2CON.1
MASTER
Read: indicates whether this device is currently as bus master.
“
XSTR
Write: writing a 1 to this bit causes a repeated start condition to be generated.
I2CON.0
—
Read: undefined.
“
XSTP
Write: writing a 1 to this bit causes a stop condition to be generated.
—
SU01155
MASTER
STP
STR
ARL
DRDY
ATN
RDAT
0
1
2
3
4
5
6
7
I2CON
Reset Value: 81h
Bit Addressable1
Address: D8h
XSTP
XSTR
CSTP
CSTR
CARL
CDR
IDLE
CXA
READ
WRITE
Figure 8. I2C Control Register (I2CON)
BIT
SYMBOL
FUNCTION
I2DAT.7
RDAT
Read: the most recently received data bit, captured from SDA at every rising edge of SCL. Reading
I2DAT also clears DRDY and the Transmit Active state.
“
XDAT
Write: sets the data for the next transmitted bit. Writing I2DAT also clears DRDY and sets the
Transmit Active state.
I2DAT.6–0
–
Unused.
—
SU01156
—
RDAT
0
1
2
3
4
5
6
7
I2DAT
Reset Value: xxh
Not Bit Addressable
Address: D9h
—
XDAT
READ
WRITE
Figure 9. I2C Data Register (I2DAT)
Checking ATN and DRDY
When a program detects ATN = 1, it should next check DRDY. If
DRDY = 1, then if it receives the last bit, it should capture the data
from RDAT (in I2DAT or I2CON). Next, if the next bit is to be sent, it
should be written to I2DAT. One way or another, it should clear
DRDY and then return to monitoring ATN. Note that if any of ARL,
STR, or STP is set, clearing DRDY will not release SCL to high, so
that the I2C will not go on to the next bit. If a program detects
ATN = 1, and DRDY = 0, it should go on to examine ARL, STR,
and STP.
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