參數(shù)資料
型號: P87LPC760BDH,118
廠商: NXP Semiconductors
文件頁數(shù): 7/56頁
文件大小: 0K
描述: IC 80C51 MCU 1KB OTP 14TSSOP
標準包裝: 2,500
系列: LPC700
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,UART/USART
外圍設備: 欠壓檢測/復位,LED,POR,WDT
輸入/輸出數(shù): 12
程序存儲器容量: 1KB(1K x 8)
程序存儲器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 6 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
包裝: 帶卷 (TR)
Philips Semiconductors
Preliminary data
P87LPC760
Low power, low price, low pin count (14 pin)
microcontroller with 1 kbyte OTP
2002 Mar 07
12
BIT
SYMBOL
FUNCTION
I2CON.7
RDAT
Read: the most recently received data bit.
CXA
Write: clears the transmit active flag.
I2CON.6
ATN
Read: ATN = 1 if any of the flags DRDY, ARL, STR, or STP = 1.
IDLE
Write: in the I2C slave mode, writing a 1 to this bit causes the I2C hardware to ignore the bus until it
is needed again.
I2CON.5
DRDY
Read: Data Ready flag, set when there is a rising edge on SCL.
CDR
Write: writing a 1 to this bit clears the DRDY flag.
I2CON.4
ARL
Read: Arbitration Loss flag, set when arbitration is lost while in the transmit mode.
CARL
Write: writing a 1 to this bit clears the CARL flag.
I2CON.3
STR
Read: Start flag, set when a start condition is detected at a master or non-idle slave.
CSTR
Write: writing a 1 to this bit clears the STR flag.
I2CON.2
STP
Read: Stop flag, set when a stop condition is detected at a master or non-idle slave.
CSTP
Write: writing a 1 to this bit clears the STP flag.
I2CON.1
MASTER
Read: indicates whether this device is currently as bus master.
XSTR
Write: writing a 1 to this bit causes a repeated start condition to be generated.
I2CON.0
Read: undefined.
XSTP
Write: writing a 1 to this bit causes a stop condition to be generated.
SU01155
MASTER
STP
STR
ARL
DRDY
ATN
RDAT
0
1
2
3
4
5
6
7
I2CON
Reset Value: 81h
Bit Addressable1
Address: D8h
XSTP
XSTR
CSTP
CSTR
CARL
CDR
IDLE
CXA
READ
WRITE
1. Due to the manner in which bit addressing is implemented in the 80C51 family, the I2CON register should never be altered by use of the
SETB, CLR, CPL, MOV (bit), or JBC instructions. This is due to the fact that read and write functions of this register are different. Testing of
I2CON bits via the JB and JNB instructions is supported.
Figure 6. I2C Control Register (I2CON)
BIT
SYMBOL
FUNCTION
I2DAT.7
RDAT
Read: the most recently received data bit, captured from SDA at every rising edge of SCL. Reading
I2DAT also clears DRDY and the Transmit Active state.
XDAT
Write: sets the data for the next transmitted bit. Writing I2DAT also clears DRDY and sets the
Transmit Active state.
I2DAT.6–0
Unused.
SU01156
RDAT
0
1
2
3
4
5
6
7
I2DAT
Reset Value: xxh
Not Bit Addressable
Address: D9h
XDAT
READ
WRITE
Figure 7. I2C Data Register (I2DAT)
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