參數(shù)資料
型號(hào)： P87C654X2
廠商： NXP Semiconductors N.V.
英文描述： Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs 20-CDIP -55 to 125
中文描述： 80C51的8位單片機(jī)系列16kB的檢察官辦公室/光盤，256B的RAM，低電壓（2.7至5.5 V），低功耗，高速（三十三分之三十〇兆赫）
文件頁(yè)數(shù)： 49/88頁(yè)
文件大小： 497K
代理商： P87C654X2
Philips Semiconductors
Product data
P83C654X2/P87C654X2
80C51 8-bit microcontroller family
16 kB OTP/ROM,
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
2004 Apr 20
49
STA FLAG
START CONDITION
(1) Unsuccessful attempt to send a Start condition
(2) SDA line released
(3) Successful attempt to send a Start condition; state 08H is entered
SDA LINE
SCL LINE
(1)
(1)
(2)
(3)
SU00977
Figure 34. Recovering from a Bus Obstruction Caused by a Low Level on SDA
Software Examples of I
2
C Service Routines:
This section
consists of a software example for:
– Initialization of I
2
C after a RESET
– Entering the I
2
C interrupt routine
– The 26 state service routines for the
– Master transmitter mode
– Master receiver mode
– Slave receiver mode
– Slave transmitter mode
I
NITIALIZATION
In the initialization routine, I
2
C is enabled for both master and slave
modes. For each mode, a number of bytes of internal data RAM are
allocated to the SIO to act as either a transmission or reception
buffer. In this example, 8 bytes of internal data RAM are reserved for
different purposes. The data memory map is shown in Figure 35.
The initialization routine performs the following functions:
– S1ADR is loaded with the part’s own slave address and the
general call bit (GC)
– P1.6 and P1.7 bit latches are loaded with logic 1s
– RAM location HADD is loaded with the high-order address byte of
the service routines
– The I
2
C interrupt enable and interrupt priority bits are set
– The slave mode is enabled by simultaneously setting the ENS1
and AA bits in S1CON and the serial clock frequency (for master
modes) is defined by loading CR0 and CR1 in S1CON. The
master routines must be started in the main program.
The I
2
C hardware now begins checking the I
2
C-bus for its own slave
address and general call. If the general call or the own slave
address is detected, an interrupt is requested and S1STA is loaded
with the appropriate state information. The following text describes a
fast method of branching to the appropriate service routine.
I
2
C I
NTERRUPT
R
OUTINE
When the I
2
C interrupt is entered, the PSW is first pushed on the
stack. Then S1STA and HADD (loaded with the high-order address
byte of the 26 service routines by the initialization routine) are
pushed on to the stack. S1STA contains a status code which is the
lower byte of one of the 26 service routines. The next instruction is
RET, which is the return from subroutine instruction. When this
instruction is executed, the HIGH and LOW order address bytes are
popped from stack and loaded into the program counter.
The next instruction to be executed is the first instruction of the state
service routine. Seven bytes of program code (which execute in
eight machine cycles) are required to branch to one of the 26 state
service routines.
SI
PUSH PSW
PUSH S1STA
Save PSW
Push status code
(low order address byte)
Push HIGH order address byte
Jump to state service routine
PUSH HADD
RET
The state service routines are located in a 256-byte page of program
memory. The location of this page is defined in the initialization
routine. The page can be located anywhere in program memory by
loading data RAM register HADD with the page number. Page 01 is
chosen in this example, and the service routines are located
between addresses 0100H and 01FFH.
T
HE
S
TATE
S
ERVICE
R
OUTINES
The state service routines are located 8 bytes from each other. Eight
bytes of code are sufficient for most of the service routines. A few of
the routines require more than 8 bytes and have to jump to other
locations to obtain more bytes of code. Each state routine is part of
the I
2
C interrupt routine and handles one of the 26 states. It ends
with a RETI instruction which causes a return to the main program.
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