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參數(shù)資料
| 型號(hào)： | P87C654X2 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs 20-CDIP -55 to 125 |
| 中文描述： | 80C51的8位單片機(jī)系列16kB的檢察官辦公室/光盤(pán)，256B的RAM，低電壓（2.7至5.5 V），低功耗，高速（三十三分之三十〇兆赫） |
| 文件頁(yè)數(shù)： | 36/88頁(yè) |
| 文件大?。?/td> | 497K |
| 代理商： | P87C654X2 |
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Philips Semiconductors
Product data
P83C654X2/P87C654X2
80C51 8-bit microcontroller family
16 kB OTP/ROM,
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
2004 Apr 20
36
If the STA and STO bits are both set, the a STOP condition is
transmitted to the I
2
C-bus if I
2
C is in a master mode (in a slave
mode, I
2
C generates an internal STOP condition which is not
transmitted). I
2
C then transmits a START condition.
STO = 0: When the STO bit is reset, no STOP condition will be
generated.
SI
,
THE
S
ERIAL
I
NTERRUPT
F
LAG
SI = 1: When the SI flag is set, then, if the EA and ES1 (interrupt
enable register) bits are also set, a serial interrupt is requested. SI is
set by hardware when one of 25 of the 26 possible I
2
C states is
entered. The only state that does not cause SI to be set is state
F8H, which indicates that no relevant state information is available.
While SI is set, the LOW period of the serial clock on the SCL line is
stretched, and the serial transfer is suspended. A HIGH level on the
SCL line is unaffected by the serial interrupt flag. SI must be reset
by software.
SI = 0: When the SI flag is reset, no serial interrupt is requested, and
there is no stretching of the serial clock on the SCL line.
AA
,
THE
A
SSERT
A
CKNOWLEDGE
F
LAG
AA = 1: If the AA flag is set, an acknowledge (low level to SDA) will
be returned during the acknowledge clock pulse on the SCL line
when:
– The “own slave address” has been received
– The general call address has been received while the general call
bit (GC) in S1ADR is set
– A data byte has been received while I
2
C is in the master receiver
mode
– A data byte has been received while I
2
C is in the addressed slave
receiver mode
AA = 0: if the AA flag is reset, a not acknowledge (HIGH level to
SDA) will be returned during the acknowledge clock pulse on SCL
when:
– A data has been received while I
2
C is in the master receiver mode
– A data byte has been received while I
2
C is in the addressed slave
receiver mode
When I
2
C is in the addressed slave transmitter mode, state C8H will
be entered after the last serial is transmitted (see Figure 31). When
SI is cleared, I
2
C leaves state C8H, enters the not addressed slave
receiver mode, and the SDA line remains at a HIGH level. In state
C8H, the AA flag can be set again for future address recognition.
When I
2
C is in the not addressed slave mode, its own slave address
and the general call address are ignored. Consequently, no
acknowledge is returned, and a serial interrupt is not requested.
Thus, I
2
C can be temporarily released from the I
2
C-bus while the
bus status is monitored. While I
2
C is released from the bus, START
and STOP conditions are detected, and serial data is shifted in.
Address recognition can be resumed at any time by setting the AA
flag. If the AA flag is set when the part’s own slave address or the
general call address has been partly received, the address will be
recognized at the end of the byte transmission.
CR
0,
CR
1,
AND
CR
2,
THE
C
LOCK
R
ATE
B
ITS
These three bits determine the serial clock frequency when I
2
C is in
a master mode. The various serial rates are shown in Table 7.
If the I
2
C block is to be used in fast mode, bit 3 in AUXR must be
set. The user can read but cannot write (write once) to AUXR after
setup.
AUXR
(8EH)
–
A0
7
6
5
4
3
2
1
0
–
–
–
FAST/
STD
I
C
–
–
A 12.5kHz bit rate may be used by devices that interface to the
I
2
C-bus via standard I/O port lines which are software driven and
slow. 100kHz is usually the maximum bit rate and can be derived
from a 16 MHz, 12 MHz, or a 6 MHz oscillator. A variable bit rate
(0.5kHz to 62.5kHz) may also be used if Timer 1 is not required for
any other purpose while I
2
C is in a master mode.
The frequencies shown in Table 7 are unimportant when I
2
C is in a
slave mode. In the slave modes, I
2
C will automatically synchronize
with any clock frequency up to 100kHz.
The Status Register, S1STA:
S1STA is an 8-bit read-only special
function register. The three least significant bits are always zero.
The five most significant bits contain the status code. There are 26
possible status codes. When S1STA contains F8H, no relevant state
information is available and no serial interrupt is requested. All other
S1STA values correspond to defined I
2
C states. When each of
these states is entered, a serial interrupt is requested (SI = 1). A
valid status code is present in S1STA one machine cycle after SI is
set by hardware and is still present one machine cycle after SI has
been reset by software.
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| P87C654X2BBD,157 | 功能描述:8位微控制器 -MCU 16K/256 OTP 12/6 CLK I2C LQFP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P87C654X2FA | 制造商:NXP Semiconductors 功能描述:P87C654X2FA 8bit microcontroller,33MHz |
| P87C654X2FA,529 | 功能描述:8位微控制器 -MCU 16K/256 OTP 12/6 CLK RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P87C654X2FA-S | 功能描述:8位微控制器 -MCU 16K/256 OTP 12/6 CLK I2C PLCC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P87C660X2BBD | 功能描述:8位微控制器 -MCU 16K/512 OTP 12/6 CLK I2C PCA RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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