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| 型號： | P87C576EHPN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| 中文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, MO-015AJ, SOT-129-1, DIP-40 |
| 文件頁數(shù)： | 6/46頁 |
| 文件大?。?/td> | 447K |
| 代理商： | P87C576EHPN |
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Philips Semiconductors
Product specification
83C576/87C576
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
1998 Jun 04
6
PIN DESCRIPTIONS
(Continued)
PIN NUMBER
MNEMONIC
+V
REF
/AV
CC
–V
REF
/AV
SS
P3.0-P3.7
DIP
1
2
LCC
2
3
QFP
40
41
TYPE
I
I
NAME AND FUNCTION
A/D positive power supply
A/D 0V reference
10-17
11,
13-19
5,
7-13
I/O
Port 3:
Port 3 is an 8-bit bidirectional I/O port. Port 3 pins that have 1s written to them can
be used as inputs but will source current when externally pulled low (see DC Electrical
Characteristics: I
). During reset all pins will be synchronously driven high and will remain
high until written to by software. Port 3 has the following output modes which can be
selected on a per bit basis by writing to P3M1 and P3M2:
P3M1.X
P3M2.X
Mode Description
0
0
Open drain. See Note 1.
0
1
Weak pullup (default). See Note 2.
1
0
High impedance. See Note 3.
1
1
Push-pull. See Note 4.
Port 3 pins serve alternate functions as follows:
P3.0
RxD
Serial receive port
P3.1
TxD
Serial transmit port (enabled only when transmitting serial data)
P3.2
INT0
External interrupt 0
CMP3+
Comparator 3 positive input
P3.3
INT1
External interrupt 1
CMP2+
Comparator 2 positive input
P3.4
T0
Timer/counter 0 input
CMP1+
Comparator 1 positive input
P3.5
T1
Timer/counter 1 input
CMPR–
Common reference to comparators 1, 2, 3
P3.6
WR
External data memory write strobe
CMP0+
Comparator 0 positive input
P3.7
RD
External data memory read strobe
CMP0–
Comparator 0 negative input
Reset:
A low on this pin synchronously resets all port pins to a high state. The pin must be
held low with the oscillator running for 24 oscillator cycles to initialize the internal registers.
An internal diffused resistor to V
CC
permits a power on reset using only an external
capacitor to V
SS
. RST has a Schmitt trigger input stage to provide additional noise immunity
with a slow rising input voltage.
Address Latch Enable/Program Pulse:
Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted at a constant rate
of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that
one ALE pulse is skipped during each access to external data memory. ALE is switched off
if the bit 0 in the AUXR register (8EH) is set. This pin is also the program pulse input
(PROG) during parallel EPROM programming. (See also Internal Reset on page 24.)
Program Store Enable:
The read strobe to external program memory. When the device is
executing code from the external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.
External Access Enable/Programming Supply Voltage:
EA must be externally held low
to enable the device to fetch code from external program memory locations 0000H to
1FFFH. If EA is held high, the device executes from internal program memory unless the
program counter contains an address greater than 1FFFH. This pin also receives the
12.75V programming supply voltage (V
) during EPROM programming. If this pin is at V
PP
voltage during reset the device enters the in-circuit programming mode.
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
Crystal 2:
Output from the inverting oscillator amplifier.
10
11
12
11
13
14
5
7
8
I
O
I
13
15
9
I
14
16
10
I
15
17
11
I
16
18
12
O
17
19
13
O
RST
9
10
4
I
ALE/PROG
30
33
27
I/O
PSEN
29
32
26
O
EA/V
PP
31
35
29
I
XTAL1
19
21
15
I
XTAL2
NOTES:
1. When Open Drain mode is selected, ports 0 and 2 have weak pulldowns to guarantee positive leakage current (see DC electrical
characteristic I
IH
).
2. When Weak Pullup mode is selected, ports bits that have 1’s written to them can be used as inputs but will source current when externally
pulled low (see DC electrical characteristic I
IL
).
3. When High Impedance mode is selected, all pullups and pulldowns are turned off. The only current sourced or sunk by the pin is the
parasitic leakage current (see DC electrical characteristic I
L2
or I
LC
, as applicable.
4. When Push-Pull mode is selected, strong pullups are on continuously when emitting 1’s (see DC electrical characteristic V
OH
).
5. When Open-Drain, Weak Pull-up, or Push-pull mode is selected.
18
20
14
O
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