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| 型號： | P87C576EHPN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer |
| 中文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, MO-015AJ, SOT-129-1, DIP-40 |
| 文件頁數(shù)： | 24/46頁 |
| 文件大?。?/td> | 447K |
| 代理商： | P87C576EHPN |
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Philips Semiconductors
Product specification
83C576/87C576
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
1998 Jun 04
24
+
+
+
+
* : WILL DISABLE PULLUPS
ON RELEVANT PINS
P3.4 / CMP1+
P3.3 / CMP2+
P3.2 / CMP3+
P3.5 / CMPR–
P3.6 / CMP0+
P3.7 / CMP0–
EC3DP *
EC2DP *
EC1DP *
EC0DP *
C3RO
C2RO
C1RO
C0RO
CMP
(C0H)
EC3TDC
EC2TDC
EC1TDC
EC0TDC
EC3OD *
EC2OD *
EC1OD *
EC0OD *
CMPE
(92H)
P2.0 / CMP0
P2.1 / CMP1
P2.2 / CMP2
P2.3 / CMP3
–
–
–
–
ENABLE
ENABLE
ENABLE
ENABLE
TO CEX0 INPUT OF
PCA MODULE 0
TO CEX1 INPUT OF
PCA MODULE 1
TO CEX2 INPUT OF
PCA MODULE 2
TO CEX3 INPUT OF
PCA MODULE 3
SU00517C
Figure 22.
Analog Comparators
INTERNAL RESET
Internal resets (see Figure 1) generated by the power on, low
voltage, software (SRST), watchdog and oscillator fail detect circuits
are self timed to guarantee proper initialization of the 8XC576. Reset
will be held approximately 24 oscillator periods after normal
conditions are detected by all enabled detect circuits. Internal resets
do not drive RST but will cause missing pulses on ALE.
Analog to Digital Converter
The 8XC576 has a 6 channel10 bit successive approximation A/D
converter with separate result registers for each channel. Operating
modes are provided for single or multiple channel conversions and
multiple conversions of a single channel without software
intervention. The ADC can also be operated in 8 bit mode with faster
conversion times. Registers ADC0H–ADC5H contain the MSBs and
ADC0L–ADC5L bits 6 and 7 contain the 2 LSBs of the conversion
result for each channel. The ADCS register determines which
channels are converted in multiple channel modes. If the ADCS bit
corresponding to a channel is set, that channel is converted, else if
the bit is clear the channel is skipped.
A/D Channel Select (ADCS) Register
ADCS5
ADCS.5 – A/D channel 5 select bit
ADCS4
ADCS.4 – A/D channel 4 select bit
ADCS3
ADCS.3 – A/D channel 3 select bit
ADCS2
ADCS.2 – A/D channel 2 select bit
ADCS1
ADCS.1 – A/D channel 1 select bit
ADCS0
ADCS.0 – A/D channel 0 select bit
(Reset Value = 00H)
A/D Control (ADCON) Register
ADF
ADCON.7 – A/D conversion complete flag
ADCE
ADCON.6 – A/D conversion enable
AD8M
ADCON.5 – A/D 8-bit mode
(Reset Value = 00H)
AMOD1 ADCON.4 – A/D mode select bit 1
AMOD0 ADCON.3 – A/D mode select bit 0
ASCA2
ADCON.2 – A/D channel address bit 2
ASCA1
ADCON.1 – A/D channel address bit 1
ASCA0
ADCON.0 – A/D channel address bit 0
AMOD1 AMOD0
0
0
Single Conversion Mode – channel selected by bits
ASCA2..0 in ADCON is converted, the result placed
in the associated result registers; ADF is set on
completion.
0
1
Mulitple Channel Scan Mode – all channels selected
in the ADCS register are converted starting with the
channel addressed by bits ASCA2..0 in ADON,
conversion results are placed in the corresponding
result registers for each channel. ADF is set when
the last conversion is completed.
1
0
Single Channel Multiple Conversion – channel
selected by bits ASCA2..0 in ADCON is converted 6
times and all 6 results are saved in ADC0H–ADC5H
and ADC0L–ADC5L, ADF is set when all
conversions are complete.
1
1
Multiple Channel Continuous – same as Multiple
Channel Scan mode but repeats as long as
ADCE=1, ADF is set when all channels have been
converted once. Hardware will prevent the ADC
from wiriting to the result registers while they are
being read.
Flag ADF is set upon completion of a conversion, if the ADC
interrupt enable bit EAD is set, the program will vector to the ADC
interrupt location when ADF is set.
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