參數(shù)資料
型號(hào): P87C557E8
廠商: NXP Semiconductors N.V.
元件分類: 8位微控制器
英文描述: 8 BIT MICROCONTROLLER
中文描述: 8位微控制器
文件頁(yè)數(shù): 22/84頁(yè)
文件大小: 322K
代理商: P87C557E8
1999 Mar 12
22
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
11.8
ADC Special Function Registers
Table 14
ADC Special Function Registers overview
The SFRs are not bit addressable. For more information on Special Function Registers refer to Section 8.2.
11.8.1
ADC R
ESULT
R
EGISTERS
The binary result code of the analog-to-digital conversions is accessed by the ADC Result Registers:
ADRSLn (ADRSL0 to ADRSL7); eight input channel related conversion result SFRs for the 8 result lower bytes. Each
of ADRSLn is associated with the indexed analog input channel ADCn (ADC0/P5.0 to ADC7/P5.7).
ADRSH for the ADC; one general SFR for the 2 result upper bits (bit 9 and 8).
During read (by software) of the ADRSLn register, simultaneously the two highest bits of the 10-bit conversion result are
copied into the two latches, ADRSH.0 and ADRSH.1 (SFR ADRSH) preserving them until the next read of any ADRSLn
register. Thus to ensure that the 10-bit result of the same single analog-to-digital conversion is captured, first read the
ADRSLn register and then the ADRSH register.
Table 15
ADC Result Register Low Byte; ADRSLn; n = 0 to 7 (address see 86H to F6H)
Table 16
Description of ADRSLn bits
ADDRESS
NAME
R/W
RESET
VALUE
DESCRIPTION
86H
96H
A6H
B6H
C6H
D6H
E6H
F6H
F7H
ADRSL0
ADRSL1
ADRSL2
ADRSL3
ADRSL4
ADRSL5
ADRSL6
ADRSL7
ADRSH
R
ADC Result Registers Low Byte: ADRSL0 to ADRSL7
; The read value
after reset is indeterminate. Their data are not affected by chip reset.
R
00H
ADC Result Register High Bits
: one common result SFR for the upper
2 result bits.
ADC Input Port Scan-Select Register
. Contains control bits to select the
analog input channel(s) to be scanned for analog-to-digital conversion.
ADC Control Register
. Contains control and status bits for the
analog-to-digital converter peripheral block.
Digital Input Port Register
; shared with analog inputs. P5 is not affected by
chip reset.
E7H
ADPSS
R/W
00H
D7H
ADCON
R/W
00H
C7H
P5
R
7
6
5
4
3
2
1
0
ADRSn.7
ADRSn.6
ADRSn.5
ADRSn.4
ADRSn.3
ADRSn.2
ADRSn.1
ADRSn.0
BIT
SYMBOL
DESCRIPTION
7 to 0
ADRSn.7 to ADRSn.0
ADC result lower byte.
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