參數(shù)資料
型號(hào)： P87C554SBBD
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
中文描述： 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 X 1.40 MM, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 67/76頁(yè)
文件大?。?/td> 400K
代理商： P87C554SBBD
Philips Semiconductors
Preliminary specification
80C554/83C554/87C554
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I
2
C, PWM,
capture/compare, high I/O, 64L LQFP
2000 Nov 10
67
Table 11. I
2
C-bus interface timing
All values referred to V
IH(min)
and V
IL(max)
levels; see Figure 56
5
.
I
2
C-BUS
SYMBOL
PARAMETER
INPUT
OUTPUT
> 4.0
μ
s
1
> 4.7
μ
s
1
> 4.0
μ
s
1
–
2
< 0.3
μ
s
3
t
HD;STA
t
LOW
t
HIGH
t
RC
t
FC
t
SU;DAT1
t
SU;DAT2
t
SU;DAT3
t
HD;DAT
t
SU;STA
t
SU;STO
t
BUF
t
RD
t
FD
START condition hold time
≥
7 t
CLK
≥
8 t
CLK
≥
7 t
CLK
≤
1
μ
s
≤
0.3
μ
s
≥
250 ns
≥
250 ns
≥
250 ns
≥
0 ns
≥
7 t
CLK
≥
7 t
CLK
≥
7 t
CLK
≤
1
μ
s
≤
0.3
μ
s
LOW period of the SCL clock
HIGH period of the SCL clock
Rise time of SCL signals
Fall time of SCL signals
Data set-up time
> 10 t
CLK
–t
RD
> 1
μ
s
1
SDA set-up time (before repeated START condition)
SDA set-up time (before STOP condition)
> 4 t
CLK
> 4 t
CLK
–t
FC
> 4.7
μ
s
1
> 4.0
μ
s
1
> 4.7
μ
s
1
–
2
< 0.3
μ
s
3
Data hold time
Set-up time for a repeated START condition
Set-up time for STOP condition
Bus free time between
Rise time of SDA signals
Fall time of SDA signals
NOTES
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1
μ
s.
3. Spikes of the SDA and SCL lines with a duration of less than 3 t
CLK
will be filtered out. Maximum capacitance on bus-lines SDA and
SCL = 400 pF.
4. t
CLK
= 1/f
CLK
= one oscillator clock period at pin XTAL1. For 83 ns < t
CLK
< 285 ns (12 MHz > f
CLK
> 3.5 MHz) the SI01 interface meets the
I
2
C-bus specification for bit-rates up to 100 kbit/s.
5. These values are guaranteed but not 100% production tested.
6. See application note AN457 for external memory interface.
7. Parts are guaranteed to operate down to 0Hz.
相關(guān)PDF資料
PDF描述
P83C554SBBD 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
P80C554SBBD 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
P87C554SFBD 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
P83C554SFBD 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
P87C554 80C51 8-bit microcontroller(80C51 8位微控制器)
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