參數(shù)資料
型號(hào): P87C552
廠商: NXP Semiconductors N.V.
英文描述: 80C51 8-bit microcontroller(80C51八位微控制器)
中文描述: 80C51的8位微控制器(80C51的八位微控制器)
文件頁數(shù): 19/74頁
文件大小: 368K
代理商: P87C552
Philips Semiconductors
Preliminary specification
P87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I
2
C, PWM,
capture/compare, high I/O, low voltage (2.7V–5.5V), low power
1999 Mar 30
19
SP40
BIT
SYMBOL
FUNCTION
STE.7
STE.6
STE.5
STE.4
STE.3
STE.2
STE.1
STE.0
TG47
TG46
SP45
SP44
SP43
SP42
SP41
SP40
Toggle flip-flops
Toggle flip-flops
If “1” then P4.5 is set on a match between CM0 and Timer T2
If “1” then P4.4 is set on a match between CM0 and Timer T2
If “1” then P4.3 is set on a match between CM0 and Timer T2
If “1” then P4.2 is set on a match between CM0 and Timer T2
If “1” then P4.1 is set on a match between CM0 and Timer T2
If “1” then P4.0 is set on a match between CM0 and Timer T2
SU01087
SP41
SP42
SP43
SP44
SP45
TG46
TG47
0
1
2
3
4
5
6
7
(LSB)
(MSB)
STE (EEH)
Reset Value = C0H
Figure 15. Set Enable Register (STE)
CTI0
BIT
SYMBOL
FUNCTION
TM2IR.7
TM2IR.6
TM2IR.5
TM2IR.4
TM2IR.3
TM2IR.2
TM2IR.1
TM2IR.0
T2OV
CMI2
CMI1
CMI0
CTI3
CTI2
CTI1
CTI0
Timer T2 16-bit overflow interrupt flag
CM2 interrupt flag
CM1 interrupt flag
CM0 interrupt flag
CT3 interrupt flag
CT2 interrupt flag
CT1 interrupt flag
CT0 interrupt flag
SU01088
CTI1
CTI2
CTI3
CMI0
CMI1
CMI2
T2OV
0
1
2
3
4
5
6
7
(LSB)
(MSB)
TM2IR (C8H)
Interrupt Flag Register (TM2IR)
PCT0
BIT
SYMBOL
FUNCTION
IP1.7
IP1.6
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
PT2
PCM2
PCM1
PCM0
PCT3
PCT2
PCT1
PCT0
Timer T2 overflow interrupt(s) priority level
Timer T2 comparator 2 interrupt priority level
Timer T2 comparator 1 interrupt priority level
Timer T2 comparator 0 interrupt priority level
Timer T2 capture register 3 interrupt priority level
Timer T2 capture register 2 interrupt priority level
Timer T2 capture register 1 interrupt priority level
Timer T2 capture register 0 interrupt priority level
PCT1
PCT2
PCT3
PCM0
PCM1
PCM2
PT2
0
1
2
3
4
5
6
7
(LSB)
(MSB)
IP1 (F8H)
Timer 2 Interrupt Priority Register (IP1)
Reset Value = 00H
Reset Value = 00H
Figure 16. Interrupt Flag Register (TM2IR) and Timer T2 Interrupt Priority Register (IP1)
相關(guān)PDF資料
PDF描述
P87C554SBBD 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
P83C554SBBD 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
P80C554SBBD 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
P87C554SFBD 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
P83C554SFBD 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
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