參數(shù)資料
型號(hào)： P87C52UBPN,112
廠商： NXP Semiconductors
文件頁數(shù)： 18/38頁
文件大?。?/td> 0K
描述： IC 80C51 MCU 256 RAM 40DIP
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝： 9
系列： 87C
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，UART/USART
外圍設(shè)備： POR
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
其它名稱： 935253730112
P87C52UBPN
P87C52UBPN-ND
Philips Semiconductors
Product specification
80C51/87C51/80C52/87C52
80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
2000 Aug 07
25
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5 V ±10%, VSS = 0 V1, 2, 3
VARIABLE CLOCK4
16 MHz to fmax
33
MHz CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
tLHLL
14
ALE pulse width
2tCLCL–40
21
ns
tAVLL
14
Address valid to ALE low
tCLCL–25
5
ns
tLLAX
14
Address hold after ALE low
tCLCL–25
ns
tLLIV
14
ALE low to valid instruction in
4tCLCL–65
55
ns
tLLPL
14
ALE low to PSEN low
tCLCL–25
5
ns
tPLPH
14
PSEN pulse width
3tCLCL–45
45
ns
tPLIV
14
PSEN low to valid instruction in
3tCLCL–60
30
ns
tPXIX
14
Input instruction hold after PSEN
0
ns
tPXIZ
14
Input instruction float after PSEN
tCLCL–25
5
ns
tAVIV
14
Address to valid instruction in
5tCLCL–80
70
ns
tPLAZ
14
PSEN low to address float
10
ns
Data Memory
tRLRH
15, 16
RD pulse width
6tCLCL–100
82
ns
tWLWH
15, 16
WR pulse width
6tCLCL–100
82
ns
tRLDV
15, 16
RD low to valid data in
5tCLCL–90
60
ns
tRHDX
15, 16
Data hold after RD
0
ns
tRHDZ
15, 16
Data float after RD
2tCLCL–28
32
ns
tLLDV
15, 16
ALE low to valid data in
8tCLCL–150
90
ns
tAVDV
15, 16
Address to valid data in
9tCLCL–165
105
ns
tLLWL
15, 16
ALE low to RD or WR low
3tCLCL–50
3tCLCL+50
40
140
ns
tAVWL
15, 16
Address valid to WR low or RD low
4tCLCL–75
45
ns
tQVWX
15, 16
Data valid to WR transition
tCLCL–30
0
ns
tWHQX
15, 16
Data hold after WR
tCLCL–25
5
ns
tQVWH
16
Data valid to WR high
7tCLCL–130
80
ns
tRLAZ
15, 16
RD low to address float
0
ns
tWHLH
15, 16
RD or WR high to ALE high
tCLCL–25
tCLCL+25
5
55
ns
External Clock
tCHCX
18
High time
0.38tCLCL
tCLCL–tCLCX
ns
tCLCX
18
Low time
0.38tCLCL
tCLCL–tCHCX
ns
tCLCH
18
Rise time
5
ns
tCHCL
18
Fall time
5
ns
Shift Register
tXLXL
17
Serial port clock cycle time
12tCLCL
360
ns
tQVXH
17
Output data setup to clock rising edge
10tCLCL–133
167
ns
tXHQX
17
Output data hold after clock rising edge
2tCLCL–80
ns
tXHDX
17
Input data hold after clock rising edge
0
ns
tXHDV
17
Clock rising edge to input data valid
10tCLCL–133
167
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the 87C51, 80C51, 87C52 or 80C52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause
damage to Port 0 drivers.
4. Variable clock is specified for oscillator frequencies greater than 16 MHz to 33 MHz. For frequencies equal or less than 16 MHz, see 16 MHz
“AC Electrical Characteristics”, page 24.
5. Parts are guaranteed to operate down to 0 Hz. When an external clock source is used, the RST pin should be held high for a minimum of
20
s for power-on or wakeup from power down.
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