80C51 8-bit microcontroller family 8KB/16KB/32KB/64K" />
參數(shù)資料
型號(hào)： P87C51RB2BBD,157
廠商： NXP Semiconductors
文件頁數(shù)： 3/67頁
文件大小： 0K
描述： IC 80C51 MCU 512 RAM 44LQFP
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝： 800
系列： 87C
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 16KB（16K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 44-LQFP
包裝： 托盤
其它名稱： 568-8732
935271877157
P87C51RB2BBD
P87C51RB2BBD,157-ND
P87C51RB2BBD-ND
Philips Semiconductors
Product data
P87C51RA2/RB2/RC2/RD2
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high
speed (30/33 MHz)
2003 Jan 24
11
CLOCK CONTROL REGISTER (CKCON)
This device allows control of the 6-clock/12-clock mode by means of
both an SFR bit (X2) and an OTP bit. The OTP clock control bit
OX2, when programmed (6-clock mode), supersedes the X2 bit
(CKCON.0). The CKCON register is shown below in Figure 1.
X2
BIT
SYMBOL
FUNCTION
CKCON.7
–
Reserved.
CKCON.6
Reserved.
CKCON.5
Reserved.
CKCON.4
Reserved.
CKCON.3
Reserved.
CKCON.2
Reserved.
CKCON.1
Reserved.
CKCON.0
X2
CPU clock; 1 = 6 clocks for each machine cycle, 0 = 12 clocks for each machine cycle
SU01689
–
Not Bit Addressable
CKCON
Address = 8Fh
Reset Value = x0000000B
76
54
321
0
––
–
Figure 1. Clock control (CKCON) register
Also please note that the clock divider applies to the serial port for
modes 0 & 2 (fixed baud rate modes). This is because modes 1 & 3
(variable baud rate modes) use either Timer 1 or Timer 2.
Below is the truth table for the CPU clock mode.
Table 1.
OX2 clock mode bit
(can only be set by
parallel programmer)
X2 bit
(CKCON.0)
CPU clock mode
erased
0
12-clock mode
(default)
erased
1
6-clock mode
programmed
X
6-clock mode
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (12 oscillator periods in 6-clock mode, or 24 oscillator
periods in 12-clock mode), while the oscillator is running. To ensure a
good power-on reset, the RST pin must be high long enough to allow
the oscillator time to start up (normally a few milliseconds) plus two
machine cycles. At power-on, the voltage on VCC and RST must
come up at the same time for a proper start-up. Ports 1, 2, and 3 will
asynchronously be driven to their reset condition when a voltage
above VIH1 (min.) is applied to RST.
The value on the EA pin is latched when RST is deasserted and has
no further effect.
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