參數(shù)資料
型號： P87C453EBAA
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller family 8K/256 OTP/ROM, expanded I/O
中文描述： 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, SOT-168-3, MO-047AE, LCC-68
文件頁數(shù)： 8/26頁
文件大?。?/td> 188K
代理商： P87C453EBAA
Philips Semiconductors
Preliminary specification
83C453/87C453
80C51 8-bit microcontroller family
8K/256 OTP/ROM, expanded I/O
1998 Apr 23
8
PX0
LSB
MSB
BIT
IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0
SYMBOL
—
POB
PIB
PS
PT1
PX1
PT0
PX0
FUNCTION
Reserved.
Defines the Output Buffer Full interrupt (IOB) priority level. POB=1 programs it to the higher priority level.
Defines the Input Buffer Full interrupt (IIB) priority level. PIB=1 programs it to the higher priority level.
Defines the Serial Port interrupt priority level. PS=1 programs it to the higher priority level.
Defines the Timer 1 interrupt priority level. PT1=1 programs it to the higher priority level.
Defines the External Interrupt 1 priority level. PX1=1 programs it to the higher priority level.
Enables or disables the Timer 0 interrupt priority level. PT0=1 programs it to the higher priority level.
Defines the External Interrupt 0 priority level. PX0=1 programs it to the higher priority level.
SU00564
PT0
PX1
PT1
PS
PIB
POB
—
Figure 3. 8XC453 Interrupt Priority (IP) Register
IDL
PCON (87H)
BIT
PCON.7
SYMBOL
SMOD1
FUNCTION
Double Baud rate bit. When set to a 1 and Timer 1 is used to generate baud rate, and the Serial Port
is used in modes 1, 2, or 3.
If set to 1, SCON.7 will be the Framing Error bit (FE). If PCON.6 is cleared, SCON.7 will be SM0.
Reserved.
Power Off Flag is set during power on of V
CC
. If then cleared by software, it can be used to determine
if a warm start has occurred.
General-purpose flag bit.
General-purpose flag bit.
Power-Down bit. Setting this bit activates power-down mode. It can only be set if input EW is high.
Idle mode bit. Setting this bit activates the idle mode.
PCON.6
PCON.5
PCON.4
SMOD0
—
POF
PCON.3
PCON.2
PCON.1
PCON.0
GF1
GF0
PD
IDL
If logic 1s are written to PD and IDL at the same time, PD takes precedence.
SU00565
PD
GF0
GF1
POF
—
SMOD2
SMOD1
0
1
2
3
4
5
6
7
Figure 4. Power Control Register (PCON)
Table 2. Interrupt Table
POLLING
PRIORITY
SOURCE
REQUEST
BITS/FLAG
VECTOR
ADDRESS
1
INTO
IE0
03H highest priority
2
Timer0
TF0
0BH
3
INT1
IE1
13H
4
Timer1
TF1
1BH
5
Port 6
OBF
33H
6
Serial I/O
RI,TI
23H
7
Port 6
IBF
2BH lowest priority
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