參數資料
型號： P87C151SB
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： HIGH-PERFORMANCE CHMOS MICROCONTROLLER
中文描述： 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數： 14/33頁
文件大小： 312K
代理商： P87C151SB
8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 8. DC Characteristics at V
CC
e
4.5V
b
5.5V
(Continued)
Symbol
Parameter
Min
Typical
Max
Units
Test Conditions
V
OH1
Output High Voltage
(Port 0 in External
Address)
V
CC
b
0.3
V
CC
b
0.7
V
CC
b
1.5
V
CC
b
0.3
V
CC
b
0.7
V
CC
b
1.5
V
I
OH
e b
200
m
A
I
OH
e b
3.2 mA
I
OH
e b
7.0 mA
I
OH
e b
200
m
A
I
OH
e b
3.2 mA
I
OH
e b
7.0 mA
V
OH2
Output High Voltage
(Port 2 in External
Address during Page
Mode)
V
I
IL
Logical 0 Input Cur-
rent (Port 1, 2, 3)
b
50
m
A
V
IN
e
0.45V
I
LI
Input Leakage Cur-
rent (Port 0)
g
10
m
A
0.45
k
V
IN
k
V
CC
I
TL
Logical 1-to-0 Transi-
tion Current (Port 1,
2, 3)
b
650
m
A
V
IN
e
2.0V
R
RST
RST Pulldown Resistor
40
225
k
X
C
IO
Pin Capacitance
10
pF
F
OSC
e
16 MHz
T
A
e
25
§
C
(Note 4)
I
PD
Powerdown Current
10
k
20
m
A
(Note 4)
I
DL
Idle Mode Current
13
20
mA
F
OSC
e
16 MHz
(Note 4)
I
CC
Operating Current
71
85
mA
F
OSC
e
16 MHz
(Note 4)
NOTES:
1. Under steady-state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin:
Maximum I
OL
per 8-bit port:
port 0
ports 1–3
Maximum Total I
OL
for
all output pins
If I
OL
exceeds the test conditions, V
OL
may exceed the related specification. Pins are not guaranteed to sink current
greater than the listed test conditions.
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4V on the low-level outputs of ALE and
ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these
signals may exceed 0.8V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input
logic.
3. Capacitive loading on ports 0 and 2 causes the V
OH
on ALE and PSEN
Y
to drop below the specification when the
address lines are stabilizing.
4. Typical values are obtained using V
CC
e
5.0, T
A
e
25
§
C and are not guaranteed.
10 mA
26 mA
15 mA
71 mA
14
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