參數(shù)資料
型號(hào)： P87C055BBP
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Microcontrollers for TV and video MTV
中文描述： 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42
文件頁(yè)數(shù)： 7/40頁(yè)
文件大?。?/td> 243K
代理商： P87C055BBP
1996 Mar 22
7
Philips Semiconductors
Product specification
Microcontrollers for TV and video (MTV)
83C145; 83C845
83C055; 87C055
Notes
1.
Port 0, Port 1 , and Port 3 pins that have logic 1s written to them float, and in that state can be used as
high-impedance inputs.
The state of the pin can always be read from the port register by the program.
P3.0, P3.4, and P3.7 can be externally pulled up as high as +12 V
±
5%; while P3.5 and P3.6 have 10 mA drive
capability.
For each PWM block, a register bit (register PWMn; bit PWnE; n = 0 to 7) controls whether the corresponding pin is
controlled by the block or by Port 0; Port 0 controls the pin immediately after a reset. Regardless of how each pin is
controlled, it can be externally pulled up as high as +12 V
±
5%.
Any of the Port 1 pins are driven LOW if the corresponding port register bit is written as a logic 0, or for P1.3 only, if
the TDAC module presents a logic 0.
2.
3.
4.
5.
HSYNC
26
Horizontal Sync
: A dedicated input for a TTL-level version of the horizontal sync
pulse. The polarity of this pulse is programmable; its trailing edge is used by the OSD
facility as the reference for horizontal positioning.
Vertical Sync
: A dedicated input for a TTL-level version of the vertical sync pulse. The
polarity of this pulse is programmable, and either edge can serve as the reference for
vertical timing.
VCLK1: Video Clock 1
; input for the horizontal timing reference for the OSD facility.
VCLK2: Video Clock 2
; output from the on-chip video oscillator. VCLK1 and VCLK2
are intended to be used with an external LC circuit to provide an on-chip oscillator. The
period of the video clock is determined such that the width of a pixel in the OSD is
equal to the inter-line separation of the raster.
Background/Foreground
: A totem-pole output which, when VCTRL is active,
indicates whether the current video data represents a Foreground (LOW) or
Background (HIGH) dot in a character. This signal can be used to reduce the intensity
of the background colour and thus emphasize the text.
XTAL1
: Input to the inverting (oscillator) amplifier and clock generator circuit that
provides the timing reference for all 83C055 logic other than the OSD facility.
XTAL2
: Oscillator output terminal for system clock. XTAL1 and XTAL2 can be used
with a quartz crystal or ceramic resonator to provide an on-chip oscillator. Alternatively,
XTAL1 can be connected to an external clock, and XTAL2 left unconnected.
Reset
: If this pin is HIGH for two machine cycles (24 oscillator periods) while the
oscillator is running, the MTV is reset. This pin is also used as a serial input to enter a
test or EPROM programming mode, as on the 87C751.
Power supply
: for normal and Power-down operation.
VSYNC
27
VCLK1
VCLK2
28
29
BF
30
XTAL1
XTAL2
31
32
RST
33
V
DD
42
SYMBOL
PIN
DESCRIPTION
相關(guān)PDF資料
PDF描述
P83C055BBP Microcontrollers for TV and video MTV
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P83C851FBA CMOS single-chip 8-bit microcontroller with on-chip EEPROM
P80C851IBA CMOS single-chip 8-bit microcontroller with on-chip EEPROM
P83C851IBP STORAGE, SLIDES CABINET RoHS Compliant: Yes
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