參數(shù)資料
型號： P87C055BBP
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Microcontrollers for TV and video MTV
中文描述： 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42
文件頁數(shù)： 35/40頁
文件大?。?/td> 243K
代理商： P87C055BBP
1996 Mar 22
35
Philips Semiconductors
Product specification
Microcontrollers for TV and video (MTV)
83C145; 83C845
83C055; 87C055
19 DC CHARACTERISTICS
V
DD
= 5 V
±
10% T
amb
= 0 to +70
°
C; all voltages with respect to V
SS
; unless otherwise specified.
Notes
1.
2.
I
DD
measured with OSD block initialized and RST remaining LOW.
This maximum applies at all times, including during power switching, and must be accounted for in power supply
design. During a Power-on process, the +12 V source used for external pull-up resistors should not precede the V
DD
of the 83C055 up their respective voltage ramps by more than this margin, nor, during a Power-down process, should
V
DD
precede +12 V down their respective voltage ramps by more than this margin.
No more than 6 (any 6) of these 10 high current outputs may be used at the V
OL1
(I
OL
= 10 mA) specification.
The other 4 should comply with the V
OL3
specification (I
OL
= 1.6 mA).
The specified current rating applies when any of these pins is used as a Pulse Width Modulated (PWM) output.
For use as a port output, the rating is as given subsequently.
The capacitance of pins P0.0 and P0.7 for the 87C055 exceeds 10 pF; for P0.0 this is maximum 40 pF, while for P0.7
it is maximum 20 pF.
3.
4.
5.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
V
DD
I
DD
V
IL
V
IL1
operating supply voltage
operating supply current
LOW level input voltage
LOW level input voltage;
VSYNC and HSYNC
HIGH level input voltage;
XTAL, VCLK1 and RST
HIGH level input voltage; P1.2 to P1.0,
P3.6 to P3.5 and P3.3 to P3.1
HIGH level input voltage;
P1.3, P3.7,P3.4 and P3.0
HIGH level input voltage; VSYNC and
HSYNC
HIGH level input voltage with respect
to V
DD
; Port 0, P1.3, P3.7, P3.4 and
P3.0
LOW level output voltage; P2.7 to P2.0
and P3.6 to P3.5
LOW level output voltage;
TDAC and PWM0 to PWM7
LOW level output voltage; all other
outputs
HIGH level output voltage;
Port 1, VID2 to VID0, VCTRL and BF
Reset (RST) pull-down resistor
Pin capacitance; except P0.0 and P0.7 test freq. = 1 MHz;
4.5
0.5
0.5
5.0
5.5
30
0.2V
DD
0.1 V
0.15V
DD
V
mA
V
DD
= 5.5 V; note 1
V
V
IH
0.7V
DD
V
DD
+ 0.5
V
V
IH1
0.2V
DD
+ 0.9
V
DD
+ 0.5
V
V
IH2
0.2V
DD
+ 0.9
12.6
V
V
IH3
0.67V
DD
V
DD
+ 0.5
V
V
IH
V
DD
note 2
0.7V
DD
V
DD
+ 0.5
V
V
OL1
I
OL
= 10 mA; note 3
0.5
V
V
OL2
I
OL
= 700
μ
A; note 4
0.5
V
V
OL3
I
OL
= 1.6 mA
0.45
V
V
OH
I
OH
=
60
μ
A
2.4
V
R
RST
C
IO
50
300
10
k
pF
T
amb
= 25
°
C; note 5
HYS
Hysteresis; VSYNC and HSYNC
0.8
V
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