參數(shù)資料
型號： P83C880
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口，同步監(jiān)測和同步處理的監(jiān)視器微控制器)
中文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42
文件頁數(shù)： 17/84頁
文件大小： 420K
代理商： P83C880
1997 Dec 12
17
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
8
INTERRUPTS
The P83C880 has 5 interrupt sources; these are shown in
Fig.6.
Interrupt INT1 is generated as in a normal 80C51 device.
By means of IT1 in SFR TCON this interrupt can be
selected to be:
Level sensitive, when IT1 = LOW; INT1 must be inactive
before a return from interrupt instruction (RETI) is given,
otherwise the same interrupt will occur again.
Edge sensitive, when IT1 = HIGH; the internal hardware
will reset the latch when the LCALL instruction is
executed for the vector address (see Table 21).
Interrupt INT0 is generated by the mode change of mode
detector. Interrupt INT0 is selected as edge or level
sensitive by the state of the IT0 bit in the SFR TCON.
However, it is recommended to always set IT0 to HIGH
(edge sensitive) so that IE0 will be reset by the internal
hardware when the LCALL instruction is executed for the
vector address.
Timer 0 and Timer 1 interrupts are generated by TF0 and
TF1 which are set by an overflow of their respective
Timer/Counter registers (except for Timer 0 in Mode 3;
see “Data Handbook IC20; 80C51 Family; Chapter
Timer/Counters”). When a timer interrupt is generated, the
interrupt flag is cleared by the internal hardware when the
LCALL instruction is executed for the vector address.
The DDC interrupt is generated either by bit SI (SFR
S1CON) for DDC2B/DDC2AB/DDC2B+ protocols or by bit
DDC_int (SFR DDCCON) or by bit SWHINT (SFR
DDCCON). These flags must be cleared by software.
All bits that generate interrupts can be set or cleared by
software, with the same result as though it had been set or
cleared by hardware. That is, interrupts can be generated
or pending interrupts can be cancelled in software.
Each of these interrupts sources can be individually
enabled or disabled by setting or clearing the bit in Special
Function Register IE (see Table 23). IE also contains a
global disable bit EA, which disables all interrupts at once.
8.1
Priority level structure
The priority level of each interrupt source can be
individually programmed by setting or clearing a bit in
Special Function Register IP (see Table 25). A low priority
interrupt can itself be interrupted by a high priority
interrupt, but not by another low priority interrupt. A high
priority interrupt can not be interrupted by another interrupt
source.
If two requests of different priority levels are received
simultaneously, the request of higher priority level is
serviced. If request of the same priority level is received
simultaneously, an internal polling sequence determines
which request is serviced. Thus within each priority level
there is a second priority structure determined as shown in
Table 21. The IP register contains a number of reserved
(in 80C51) bits: IP.7, IP.6 and IP.4. User software should
not write logic 1s to these positions, since they may be
used in other 80C51 family products.
Table 21
Priority within levels
Note
1.
The ‘Priority within level’ structure is only used to
resolve simultaneous requests of the same priority
level.
SOURCE
IE0
′
SI
TF0
IE1
′
TF1
PRIORITY WITHIN LEVEL
(1)
1 (highest)
2
3
4
5 (lowest)
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