參數(shù)資料
          型號(hào): P83C660X2FA
          廠商: NXP SEMICONDUCTORS
          元件分類: 微控制器/微處理器
          英文描述: 80C51 8-bit microcontroller family
          中文描述: 8-BIT, MROM, 33 MHz, MICROCONTROLLER, PQCC44
          封裝: PLASTIC, MS-018, SOT-187-2, LCC-44
          文件頁數(shù): 86/102頁
          文件大小: 584K
          代理商: P83C660X2FA
          Philips Semiconductors
          Product data
          P8xC660X2/661X2
          80C51 8-bit microcontroller family
          16 KB OTP/ROM, 512B
          RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
          MHz), two 400KB I
          2
          C interfaces
          2003 Oct 02
          86
          AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE, 2.7 V TO 5.5 V OPERATION)
          T
          amb
          = 0
          °
          C to +70
          °
          C or –40
          °
          C to +85
          °
          C ; V
          CC
          =2.7 V to 5.5 V, V
          SS
          = 0 V
          1,2,3,4,5
          Symbol
          Figure
          Parameter
          Limits
          MIN
          16 MHz Clock
          MIN
          Unit
          MAX
          MAX
          1/t
          CLCL
          t
          LHLL
          t
          AVLL
          t
          LLAX
          t
          LLIV
          t
          LLPL
          t
          PLPH
          t
          PLIV
          t
          PXIX
          t
          PXIZ
          t
          AVIV
          t
          PLAZ
          Data Memory
          t
          RLRH
          t
          WLWH
          t
          RLDV
          t
          RHDX
          t
          RHDZ
          t
          LLDV
          t
          AVDV
          t
          LLWL
          t
          AVWL
          t
          QVWX
          t
          WHQX
          t
          QVWH
          t
          RLAZ
          t
          WHLH
          External Clock
          t
          CHCX
          t
          CLCX
          t
          CLCH
          t
          CHCL
          Shift register
          t
          XLXL
          t
          QVXH
          t
          XHQX
          t
          XHDX
          t
          XHDV
          55
          50
          50
          50
          50
          50
          50
          50
          50
          50
          50
          50
          Oscillator frequency
          ALE pulse width
          Address valid to ALE LOW
          Address hold after ALE LOW
          ALE LOW to valid instruction in
          ALE LOW to PSEN LOW
          PSEN pulse width
          PSEN LOW to valid instruction in
          Input instruction hold after PSEN
          Input instruction float after PSEN
          Address to valid instruction in
          PSEN LOW to address float
          0
          t
          CLCL
          –10
          0.5 t
          CLCL
          –15
          0.5 t
          CLCL
          –25
          16
          MHz
          ns
          ns
          ns
          ns
          ns
          ns
          ns
          ns
          ns
          ns
          ns
          52.5
          16.25
          6.25
          2 t
          CLCL
          –55
          70
          0.5 t
          CLCL
          –15
          1.5 t
          CLCL
          –15
          16.25
          78.75
          1.5 t
          CLCL
          –55
          38.75
          0
          0
          0.5 t
          CLCL
          –10
          2.5 t
          CLCL
          –50
          10
          21.25
          101.25
          10
          51
          52
          51
          51
          51
          51
          51
          51, 52
          51, 52
          52
          52
          52
          51
          51, 52
          RD pulse width
          WR pulse width
          RD LOW to valid data in
          Data hold after RD
          Data float after RD
          ALE LOW to valid data in
          Address to valid data in
          ALE LOW to RD or WR LOW
          Address valid to WR LOW or RD LOW
          Data valid to WR transition
          Data hold after WR
          Data valid to WR HIGH
          RD LOW to address float
          RD or WR HIGH to ALE HIGH
          3 t
          CLCL
          –25
          3 t
          CLCL
          –25
          162.5
          162.5
          ns
          ns
          ns
          ns
          ns
          ns
          ns
          ns
          ns
          ns
          ns
          ns
          ns
          ns
          2.5 t
          CLCL
          –50
          106.25
          0
          0
          t
          CLCL
          –20
          4 t
          CLCL
          –55
          4.5 t
          CLCL
          –50
          1.5 t
          CLCL
          +20
          42.5
          195
          231.25
          113.75
          1.5 t
          CLCL
          –20
          2 t
          CLCL
          –20
          0.5 t
          CLCL
          –30
          0.5 t
          CLCL
          –20
          3.5 t
          CLCL
          –10
          73.75
          105
          1.25
          11.25
          208.75
          0
          0.5 t
          CLCL
          +15
          0
          46.25
          0.5 t
          CLCL
          –15
          16.25
          55
          55
          55
          55
          High time
          Low time
          Rise time
          Fall time
          0.4 t
          CLCL
          0.4 t
          CLCL
          t
          CLCL
          – t
          CLCX
          t
          CLCL
          – t
          CHCX
          5
          5
          ns
          ns
          ns
          ns
          54
          54
          54
          54
          54
          Serial port clock cycle time
          Output data setup to clock rising edge
          Output data hold after clock rising edge
          Input data hold after clock rising edge
          Clock rising edge to input data valid
          6
          6 t
          CLCL
          5 t
          CLCL
          –25
          t
          CLCL
          –15
          0
          375
          287.5
          47.5
          0
          ns
          ns
          ns
          ns
          ns
          5 t
          CLCL
          –133
          179.5
          NOTES:
          1. Parameters are valid over operating temperature range unless otherwise specified.
          2. Load capacitance for port 0, ALE, and PSEN=100 pF, load capacitance for all outputs = 80 pF
          3. Interfacing the microcontroller to devices with float time up to 45ns is permitted. This limited bus contention will not cause damage to port 0
          drivers.
          4. Parts are guaranteed by design to operate down to 0 Hz.
          5. Data shown in the table are the best mathematical models for the set of measured values obtained in tests. If a particular parameter
          calculated at a customer specified frequency has a negative value, it should be considered equal to zero.
          6. Below 16 MHz this parameter is 4 t
          CLCL
          – 133
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