參數(shù)資料
型號(hào): P83C660X2FA
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 80C51 8-bit microcontroller family
中文描述: 8-BIT, MROM, 33 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, MS-018, SOT-187-2, LCC-44
文件頁數(shù): 32/102頁
文件大?。?/td> 584K
代理商: P83C660X2FA
Philips Semiconductors
Product data
P8xC660X2/661X2
80C51 8-bit microcontroller family
16 KB OTP/ROM, 512B
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I
2
C interfaces
2003 Oct 02
32
of the receiving device (7 bytes) and the data direction bit. In this
case the data direction bit (R/W) will be logic 0, and we say that
a “W” is transmitted. Thus the first byte transmitted is SLA+W.
Serial data is transmitted 8 bits at a time. After each byte is
transmitted, an acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the end of a
serial transfer.
2. Master Receiver Mode:
The first byte transmitted contains the slave address of
the transmitting device (7 bits) and the data direction bit. In this
case, the data direction bit (R/W) will be logic 1, and we say that
an “R” is transmitted. Thus the first byte transmitted is SLA+R.
Serial data is received via P1.7/SDA while P1.6/SCL outputs the
serial clock. Serial data is received 8 bits at a time. After each
byte is received an acknowledge bit is transmitted. START and
STOP conditions are output to indicate the beginning and end of
a serial transfer.
3. Slave Receiver Mode:
Serial data and the serial clock are received through P1.7/SDA
and P1.6/SCL. After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is
performed by hardware after reception of the slave address and
direction bit.
4. Slave Transmitter Mode:
The first byte is received and handled as in the slave receiver
mode. However, in this mode, the direction bit will indicate that
the transfer direction is reversed. Serial data is transmitted via
P1.7/SDA while the serial clock is input through P1.6/SCL.
START and STOP conditions are recognized as the beginning
and end of a serial transfer.
In a given application, SIO1 may operate as a master and as a
slave. In the slave mode, the SIO1 hardware looks for its own slave
address and the general call address. If one of these addresses is
detected, an interrupt is requested. When the microcontroller wishes
to become the bus master, the hardware waits until the bus is free
before the master mode is entered so that a possible slave action is
not interrupted. If bus arbitration is lost in the master mode, SIO1
switches to the slave mode immediately and can detect its own
slave address in the same serial transfer.
V
DD
OTHER DEVICE WITH
I
C INTERFACE
P8xC66xX2
OTHER DEVICE WITH
I
C INTERFACE
P1.7/SDA
P1.6/SCL
SDA
SCL
I
2
C bus
R
P
R
P
SU01748
Figure 15. Typical I
2
C Bus Configuration
SCL
START
CONDITION
S
SDA
P/S
MSB
ACKNOWLEDGMENT
SIGNAL FROM RECEIVER
CLOCK LINE HELD LOW WHILE
INTERRUPTS ARE SERVICED
1
2
7
8
9
1
2
3–8
ACK
9
ACK
REPEATED IF MORE BYTES
ARE TRANSFERRED
ACKNOWLEDGMENT
SIGNAL FROM RECEIVER
SLAVE ADDRESS
R/W
DIRECTION
BIT
STOP
CONDITION
REPEATED
START
CONDITION
SU00965
Figure 16. Data Transfer on the I
2
C Bus
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