參數(shù)資料
型號(hào)： P83C654IFB
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： CMOS single-chip 8-bit microcontroller
中文描述： 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP44
文件頁(yè)數(shù)： 48/88頁(yè)
文件大?。?/td> 497K
代理商： P83C654IFB
Philips Semiconductors
Product data
P83C654X2/P87C654X2
80C51 8-bit microcontroller family
16 kB OTP/ROM,
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
2004 Apr 20
48
S
08H
SLA
W
A
DATA
A
S
BOTH MASTERS CONTINUE
WITH SLA TRANSMISSION
18H
28H
OTHER MASTER SENDS REPEATED
START CONDITION EARLIER
SU00975
Figure 32. Simultaneous Repeated START Conditions from 2 Masters
STA FLAG
TIME OUT
SDA LINE
SCL LINE
START CONDITION
SU00976
Figure 33. Forced Access to a Busy I
2
C-bus
I
2
C
-BUS
O
BSTRUCTED
BY
A
L
OW
L
EVEL
ON
SCL
OR
SDA
An I
2
C-bus hang-up occurs if SDA or SCL is pulled LOW by an
uncontrolled source. If the SCL line is obstructed (pulled LOW) by a
device on the bus, no further serial transfer is possible, and the I
2
C
hardware cannot resolve this type of problem. When this occurs, the
problem must be resolved by the device that is pulling the SCL bus
line LOW.
If the SDA line is obstructed by another device on the bus (e.g., a
slave device out of bit synchronization), the problem can be solved
by transmitting additional clock pulses on the SCL line (see Figure
34). The I
2
C hardware transmits additional clock pulses when the
STA flag is set, but no START condition can be generated because
the SDA line is pulled LOW while the I
2
C-bus is considered free.
The I
2
C hardware attempts to generate a START condition after
every two additional clock pulses on the SCL line. When the SDA
line is eventually released, a normal START condition is transmitted,
state 08H is entered, and the serial transfer continues.
If a forced bus access occurs or a repeated START condition is
transmitted while SDA is obstructed (pulled LOW), the I
2
C hardware
performs the same action as described above. In each case, state
08H is entered after a successful START condition is transmitted
and normal serial transfer continues. Note that the CPU is not
involved in solving these bus hang-up problems.
B
US
E
RROR
A bus error occurs when a START or STOP condition is present at
an illegal position in the format frame. Examples of illegal positions
are during the serial transfer of an address byte, a data or an
acknowledge bit.
The I
2
C hardware only reacts to a bus error when it is involved in a
serial transfer either as a master or an addressed slave. When a
bus error is detected, I
2
C immediately switches to the not addressed
slave mode, releases the SDA and SCL lines, sets the interrupt flag,
and loads the status register with 00H. This status code may be
used to vector to a service routine which either attempts the aborted
serial transfer again or simply recovers from the error condition as
shown in Table 13.
相關(guān)PDF資料
PDF描述
P83C654IFBB LAN Tester
P83C654IFP CMOS single-chip 8-bit microcontroller
P83C654IFPN CMOS single-chip 8-bit microcontroller
P83C654IBP CMOS single-chip 8-bit microcontroller
P83C654IBPN CONNECTOR ACCESSORY
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
P83C654IFBB 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CMOS single-chip 8-bit microcontroller
P83C654IFP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CMOS single-chip 8-bit microcontroller
P83C654IFPN 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CMOS single-chip 8-bit microcontroller
P83C654X2 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 16 kB OTP/ROM, 256B RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P83C654X2BBD 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:80C51 8-bit microcontroller family 16 kB OTP/ROM, 256B RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
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