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參數(shù)資料
| 型號： | P83C654EHBB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS single-chip 8-bit microcontroller |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 X 1.75 MM, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 30/88頁 |
| 文件大小： | 497K |
| 代理商： | P83C654EHBB |
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Philips Semiconductors
Product data
P83C654X2/P87C654X2
80C51 8-bit microcontroller family
16 kB OTP/ROM,
256B RAM, low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
2004 Apr 20
30
I
2
C-bus Serial I/O
The I
2
C-bus serial port is identical to the I
2
C-bus serial port on the
8xC554 and 8xC652 devices.
Note that in the P8xC654X2, the I
2
C-bus pins are alternate functions
to port pins P1.6 and P1.7. Because of this, P1.6 and P1.7 on these
parts do not have a pull-up structure as found on the 80C51; P1.6
and P1.7 have open drain outputs.
The I
2
C-bus uses two wires (SDA and SCL) to transfer information
between devices connected to the bus. The main features of the bus
are:
– Bidirectional data transfer between masters and slaves
– Multimaster bus (no central master)
– Arbitration between simultaneously transmitting masters without
corruption of serial data on the bus
– Serial clock synchronization allows devices with different bit rates
to communicate via one serial bus
– Serial clock synchronization can be used as a handshake
mechanism to suspend and resume serial transfer
– The I
2
C-bus may be used for test and diagnostic purposes
The output latches of P1.6 and P1.7 must be set to logic 1 in order
to enable I
2
C-bus.
The P8xC654X2 on-chip I
2
C-bus logic provides a serial interface
that meets the I
2
C-bus specification and supports all transfer modes
(other than the low-speed mode) from and to the I
2
C-bus. The
I
2
C-bus logic handles bytes transfer autonomously. It also keeps
track of serial transfers, and a status register (S1STA) reflects the
status of the I
2
C-bus.
The CPU interfaces to the I
2
C-bus logic via the following four special
function registers: S1CON (I
2
C-bus control register), S1STA
(I
2
C-bus status register), S1DAT (I
2
C-bus data register), and
S1ADR (I
2
C-bus slave address register). The I
2
C-bus logic
interfaces to the external I
2
C-bus via two port 1 pins: P1.6/SCL
(serial clock line) and P1.7/SDA (serial data line).
A typical I
2
C-bus configuration is shown in Figure 21, and Figure 22
shows how a data transfer is accomplished on the bus. Depending
on the state of the direction bit (R/W), two types of data transfers are
possible on the I
2
C-bus:
1. Data transfer from a master transmitter to a slave receiver. The
first byte transmitted by the master is the slave address. Next
follows a number of data bytes. The slave returns an
acknowledge bit after each received byte.
2. Data transfer from a slave transmitter to a master receiver. The
first byte (the slave address) is transmitted by the master. The
slave then returns an acknowledge bit. Next follows the data
bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last
byte. At the end of the last received byte, a “not acknowledge” is
returned.
The master device generates all of the serial clock pulses and the
START and STOP conditions. A transfer is ended with a STOP
condition or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial transfer, the
I
2
C-bus will not be released.
Modes of Operation:
The on-chip I
2
C-bus logic may operate in the
following four modes:
1. Master Transmitter Mode:
Serial data output through P1.7/SDA while P1.6/SCL outputs the
serial clock. The first byte transmitted contains the slave address
of the receiving device (7 bits) and the data direction bit. In this
case the data direction bit (R/W) will be logic 0, and we say that
a “W” is transmitted. Thus the first byte transmitted is SLA+W.
Serial data is transmitted 8 bits at a time. After each byte is
transmitted, an acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the end of a
serial transfer.
2. Master Receiver Mode:
The first byte transmitted contains the slave address of the
transmitting device (7 bits) and the data direction bit. In this case
the data direction bit (R/W) will be logic 1, and we say that an “R”
is transmitted. Thus the first byte transmitted is SLA+R. Serial
data is received via P1.7/SDA while P1.6/SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each byte is
received, an acknowledge bit is transmitted. START and STOP
conditions are output to indicate the beginning and end of a
serial transfer.
3. Slave Receiver Mode:
Serial data and the serial clock are received through P1.7/SDA
and P1.6/SCL. After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is
performed by hardware after reception of the slave address and
direction bit.
4. Slave Transmitter Mode:
The first byte is received and handled as in the slave receiver
mode. However, in this mode, the direction bit will indicate that
the transfer direction is reversed. Serial data is transmitted via
P1.7/SDA while the serial clock is input through P1.6/SCL.
START and STOP conditions are recognized as the beginning
and end of a serial transfer.
In a given application, I
2
C-bus may operate as a master and as a
slave. In the slave mode, the I
2
C-bus hardware looks for its own
slave address and the general call address. If one of these
addresses is detected, an interrupt is requested. When the
microcontroller wishes to become the bus master, the hardware
waits until the bus is free before the master mode is entered so that
a possible slave action is not interrupted. If bus arbitration is lost in
the master mode, the I
2
C-bus switches to the slave mode
immediately and can detect its own slave address in the same serial
transfer.
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相關代理商/技術參數(shù) |
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| P83C654EHP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CMOS single-chip 8-bit microcontroller |
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