參數(shù)資料
型號： P83C592FFA
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Single-chip 8-bit microcontroller with CAN controller(帶CAN控制器的單片8位微控制器)
中文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, SOT-168-3, MO-047AE, LCC-68
文件頁數(shù)： 44/108頁
文件大小： 650K
代理商： P83C592FFA
1996 Jun 27
44
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xC592
13.5.11 O
UTPUT
C
ONTROL
R
EGISTER
(OCR)
The Output Control Register allows, under software
control, the set-up of different output driver configurations.
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present). If the CAN-controller is
in the sleep mode (Sleep = HIGH) a recessive level is
output on the CTX0 and CTX1 pins. If the CAN-controller
is in the reset state (Reset Request = HIGH) the output
drivers are floating.
Tables 50 and 51, show the relationship between the bits
of the Output Control Register and the two serial output
pins CTX0 and CTX1 of the P8xC592 CAN-controller,
connected to the serial bus (see Fig.14).
Table 49
Output Control Register (address 8)
Table 50
Description of the OCR bits
Table 51
Description of the Output Mode bits
7
6
5
4
3
2
1
0
OCTP1
OCTN1
OCPOL1
OCTP0
OCTN0
OCPOL0
OCMODE1
OCMODE0
BIT
SYMBOL
FUNCTION
7
6
5
4
3
2
1
0
OCTP1
OCTN1
OCPOL1
OCTP0
OCTN0
OCPOL0
OCMODE1
Output Mode
.
These bits select the output mode; see Table 51.
OCMODE0
See Tables 51 and 52.
OCMODE1 OCMODE0
DESCRIPTION
1
0
Normal Output Mode
. The bit sequence (TXD) is sent via CTX0, CTX1. TXD is the data
bit to be transmitted. The voltage levels on the output driver pins CTX0 and CTX1 depend
on both the driver characteristic programmed by OCTPx, OCTNx (float, pull-up, pull-down,
push-pull) and the output polarity programmed by OCPOLx (see Fig.17).
Clock Output Mode
. For the CTX0 pin this is the same as in Normal Output Mode
(CTX0: bit sequence). However, the data stream to CTX1 is replaced by the transmit clock
(TXCLK). The rising edge of the transmit clock (non-inverted) marks the beginning of a bit
period. The clock pulse width is t
SCL
.
Bi-phase Output Mode
. In contrast to Normal Output Mode the bit representation is time
variant and toggled. If the bus controllers are galvanically decoupled from the bus-line by a
transformer, the bit stream is not allowed to contain a DC component. This is achieved by
the following scheme. During recessive bits all outputs are deactivated (floating). Dominant
bits are sent alternately on CTX0 and CTX1, i.e. the first dominant bit is sent on CTX0, the
second is sent on CTX1, and the third one is sent on CTX0 again, etc.
Test Output Mode.
For the CTX0 pin this is the same as in Normal Output Mode
(CTX0: bit sequence). To measure the delay time of the transmitter and receiver this mode
connects the output of the input comparator (COMP OUT) with the input of the output driver
CTX1. This mode is used for production testing only.
1
1
0
0
0
1
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