參數(shù)資料
型號: P83C592FFA
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single-chip 8-bit microcontroller with CAN controller(帶CAN控制器的單片8位微控制器)
中文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC68
封裝: PLASTIC, SOT-168-3, MO-047AE, LCC-68
文件頁數(shù): 42/108頁
文件大?。?/td> 650K
代理商: P83C592FFA
1996 Jun 27
42
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xC592
13.5.9
B
US
T
IMING
R
EGISTER
0 (BTR0)
The contents of Bus Timing Register 0 defines the values
of the Baud Rate Prescaler (BRP) and the Synchronization
Jump Width (SJW).
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present).
For further information on bus timing, see
Sections 13.5.10 and 13.5.18.
Table 45
Bus Timing Register 0 (address 6)
Table 46
Description of the BTR0 bits
7
6
5
4
3
2
1
0
SJW.1
SJW.0
BRP.5
BRP.4
BRP.3
BRP.2
BRP.1
BRP.0
BIT SYMBOL
FUNCTION
7
6
SJW.1
SJW.0
Synchronization Jump Width.
To compensate for phase shifts between clock oscillators of different
bus controllers, any bus controller must resynchronize on any relevant signal edge of the current
transmission. The synchronization jump width defines the maximum number of clock cycles a bit
period may be shortened or lengthened by one resynchronization:
t
SJW
t
SCL
2SJW.1
SJW.0
1
+
+
=
5
4
3
2
1
0
BRP.5
BRP.4
BRP.3
BRP.2
BRP.1
BRP.0
Baud Rate Prescaler.
The period of the system clock t
SCL
is programmable and determines the
individual bit timing.The system clock is calculated using the following equation:
t
SCL
2t
CLK
32BRP.5
16BRP.4
8BRP.3
+
+
+
=
.
Where t
CLK
= time period of the P8xC592 oscillator.
(
)
.
˙˙
4BRP.2
2BRP.1
BRP.0
1
+
+
+
(
)
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