參數(shù)資料
型號(hào)： P83C591SFB
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Single-chip 8-bit microcontroller with CAN controller
中文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 X 1.75 MM, PLASTIC, SOT-307-2, QFP-44
文件頁數(shù)： 38/161頁
文件大小： 588K
代理商： P83C591SFB
1999 Aug 19
38
Philips Semiconductors
Objective Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
12.5.5
I
NTERRUPT
R
EGISTER
(IR)
The Interrupt Register allows the identification of an interrupt source. When one or more bits of this register are set, a
CAN interrupt will be indicated to the CPU. After this register is read by the CPU all bits are reset except of the Receive
Interrupt bit.
The Interrupt Register appears to the CPU as a read only memory.
Table 16
Interrupt Register (IR) CAN Addr. 3, bit interpretation
BIT
SYMBOL
NAME
VALUE
FUNCTION
IR.7
BEI
Bus Error Interrupt
1 (set)
This bit is set when the CAN Controller detects an error on
the CAN Bus and the BEIE bit is set within the Interrupt
Enable Register. After a bus error interrupt event this
interrupt is locked until the Error Code Capture Register is
read out once.
0 (reset)
1 (set)
IR.6
ALI
Arbitration Lost
Interrupt
This bit is set when the CAN Controller has lost arbitration
and becomes a receiver and the ALIE bit is set within the
Interrupt Enable Register. After an arbitration lost interrupt
event this interrupt is locked until the Arbitration Lost Capture
Register is read out once.
0 (reset)
1 (set)
IR.5
EPI
Error Passive
Interrupt
This bit is set whenever the CAN Controller has reached the
Error Passive Status (at least one error counter exceeds the
CAN protocol defined level of 127) or if the CAN Controller is
in Error Passive Status and enters the Error Active Status
again and the EPIE bit is set within the Interrupt Enable
Register.
0 (reset)
1 (set)
IR.4
WUI
Wake-Up Interrupt;
Note 1
This bit is set when the CAN Controller is sleeping and bus
activity is detected and the WUIE bit is set within the
Interrupt Enable Register.
0 (reset)
1 (set)
IR.3
DOI
Data Overrun
Interrupt
This bit is set on a 0-to-1 change of the Data Overrun Status
bit, when the Data Overrun Interrupt Enable is set to ‘1’
(enabled).
0 (reset)
1 (set)
IR.2
EI
Error Interrupt
This bit is set on every change (set and clear) of either the
Error Status or Bus Status bits if the Error Interrupt Enable is
set to ‘1’ (enabled).
0 (reset)
1 (set)
IR.1
TI
Transmit Interrupt;
Note 2
This bit is set whenever the Transmit Buffer Status changes
from ‘0’ to ‘1’ (released) and Transmit Interrupt Enable is set
to ‘1’ (enabled).
0 (reset)
1 (set)
IR.0
RI
Receive Interrupt;
Note 4
This bit is set whenever the RXFIFO is filled with more bytes
than specified in the Rx Interrupt Level register or a message
has passed an acceptance filter which is set to “high priority”
and the RIE bit is set within the Interrupt Enable Register.
0 (reset)
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