參數(shù)資料
型號(hào)： P83C575EBBB
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
中文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
封裝： PLASTIC, SOT-307-2, QFP-44
文件頁(yè)數(shù)： 17/40頁(yè)
文件大?。?/td> 383K
代理商： P83C575EBBB
Philips Semiconductors
Product specification
80C575/83C575/
87C575
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
1998 May 01
17
period, N is the selected prescaler tap value,
W is the main counter autoload value, t
MIN
is
the minimum watchdog time-out value (when
the autoload value is 0), t
MAX
is the maximum
time-out value (when the autoload value is
FFH), t
D
is the design time-out value.
t
MIN
= t
OSC
×
12
×
64
t
MAX
= t
MIN
×
128
×
256
t
D
= t
MIN
×
2
PRESCALER
×
(W + 1)
(where prescaler = 0, 1, 2, 3, 4, 5, 6, or 7)
Note that the design procedure is anticipated
to be as follows. A t
MAX
will be chosen either
from equipment or operation considerations
and will most likely be the next convenient
value higher than t
D
. (If the watchdog were
inadvertently to start from FFH, an overflow
would be guaranteed, barring other
anomalies, to occur within t
MAX
). Then the
value for the prescaler would be chosen
from:
prescaler = log2 (t
MAX
/ (t
OSC
×
12
×
256)) - 6
This then also fixes t
MIN
. An autoload value
would then be chosen from:
W = t
D
/ t
MIN
- 1
The software must be written so that a feed
operation takes place every t
D
seconds from
the last feed operation. Some tradeoffs may
need to be made. It is not advisable to
include feed operations in minor loops or in
subroutines unless the feed operation is a
specific subroutine.
Watchdog Control Register (WDCON)
(Bit Addressable) Address C0
The following bits of this register are read
only in the ROM part when EA is high:
WDMOD, PRE0, PRE1, and PRE2. That is,
the register will reflect the mask programmed
values. In the ROM part with EA high, these
bits are taken from mask coded bits and are
not readable by the program. WDRUN is
read only in the ROM part when EA is high
and WDMOD is in the watchdog mode. When
WDMOD is in the timer mode, WDRUN
functions normally.
The parameters written into WDMOD, PRE0,
PRE1, and PRE2 by the program are not
applied directly to the watchdog timer
subsystem. The watchdog timer subsystem is
directly controlled by a second register which
stores these bits. The transfer of these bits
from the user register (WDMOD) to the
second control register takes place when the
watchdog is fed. This prevents random code
execution from directly foiling the watchdog
function. This does not affect the operation
where these bits are taken from mask coded
values.
The reset values of the WDCON and WDL
registers will be such that the timer resets to
the watchdog mode with a timeout period of
12
×
64
×
128
×
t
OSC
. The watchdog timer
will not generate an interrupt. Additional bits
in WDCON are used to disable reset
generation by the oscillator fail and low
voltage detect circuits. WDCON can be
written by software only by executing a valid
watchdog feed sequence.
WDCON Register Bit Definitions
WDCON.7
PRE2
Prescaler Select 2,
reset to 1
Prescaler Select 1,
reset to 1
Prescaler Select 0,
reset to 1
Low Voltage Reset
Enable, reset to 1
(enabled)
Oscillator Fail Reset
Enable, reset to 1
(enabled)
Watchdog Run,
reset to 1 (enabled)
Watchdog Timeout
Flag, reset =
Indeterminate
Watchdog Mode,
reset to 1 (watchdog
mode)
WDCON.6
PRE1
WDCON.5
PRE0
WDCON.4
LVRE
WDCON.3
OFRE
WDCON.2
WDRUN
WDCON.1
WDTOF
WDCON.0
WDMOD
Enhanced UART
The UART operates in all of the usual modes
that are described in the first section of this
book for the 80C51. In addition the UART can
perform framing error detect by looking for
missing stop bits, and automatic address
recognition. The 87C575 UART also fully
supports multiprocessor communication as
does the standard 80C51 UART.
When used for framing error detect the UART
looks for missing stop bits in the
communication. A missing bit will set the FE
bit in the SCON register. The FE bit shares
the SCON.7 bit with SM0 and the function of
SCON.7 is determined by PCON.6 (SMOD0)
(see Figure 19). If SMOD0 is set then
SCON.7 functions as FE. SCON.7 functions
as SM0 when SMOD0 is cleared. When used
as FE SCON.7 can only be cleared by
software. Refer to Figure 18.
Automatic Address Recognition
Automatic Address Recognition is a feature
which allows the UART to recognize certain
addresses in the serial bit stream by using
hardware to make the comparisons. This
feature saves a great deal of software
overhead by eliminating the need for the
software to examine every serial address
which passes by the serial port. This feature
is enabled by setting the SM2 bit in SCON. In
the 9 bit UART modes, mode 2 and mode 3,
the Receive Interrupt flag (RI) will be
automatically set when the received byte
contains either the “Given” address or the
“Broadcast” address. The 9 bit mode requires
that the 9th information bit is a 1 to indicate
that the received information is an address
and not data. Automatic address recognition
is shown in Figure 20.
The 8 bit mode is called Mode 1. In this mode
the RI flag will be set if SM2 is enabled and
the information received has a valid stop bit
following the 8 address bits and the
information is either a Given or Broadcast
address.
Mode 0 is the Shift Register mode and SM2
is ignored.
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