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參數(shù)資料
| 型號(hào)： | P83C566BDR |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers for PAL/SECAM TV with OSD and VST |
| 中文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SDIP-42 |
| 文件頁數(shù)： | 21/92頁 |
| 文件大小： | 382K |
| 代理商： | P83C566BDR |
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1999 Mar 10
21
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
10.5
Data Shift Register (S1DAT)
S1DAT contains the serial data to be transmitted or data that has just been received. Bit 7 is transmitted or received first.
Table 13
Data Shift Register (SFR address DAH)
10.6
Slave Address Register (S1ADR)
This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as
slave receiver/transmitter. The LSB bit (GC) is used to determine whether the general CALL address is recognized.
Table 14
Slave Address Register (SFR address DBH)
Table 15
Description of S1ADR bits
10.7
Internal Status Register (S1IST)
S1IST is an 8-bit read-only Special Function Register and will exist in the design but is not mapped for the user.
Table 16
Internal Status Register (SFR address DCH)
10.8
I
2
C-bus Control Register (I
2
CCON)
Table 17
I
2
C-bus Control Register (SFR address 86H)
Table 18
Description of I
2
CCON bits
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
7
6
5
4
3
2
1
0
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
SLA0
GC
BIT
SYMBOL
DESCRIPTION
7 to 1
SLA6 to
SLA0
GC
Own slave address.
0
When GC = 0, the general CALL address is not recognized. When GC = 1, the general
CALL address is recognized.
7
6
5
4
3
2
1
0
MST
TRX
BB
FB
ARL
SEL
AD0
SHRA
7
6
5
4
3
2
1
0
I
2
CE
BIT
SYMBOL
DESCRIPTION
7 to 3
2
I
2
CE
These 5 bits are not used.
I
2
C-bus enable.
This bit selects the functions of pins 39 and 40 for the SDIP42 package
(or pins 64 and 65 for the PLCC68 package). When I
2
CE = 1, the alternative functions
SCL and SDA are selected. When I
2
CE = 0, these pins act as port lines P1.5 and P1.6.
These bits are not used.
1 to 0
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