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| 型號(hào)： | P83C566BDR |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers for PAL/SECAM TV with OSD and VST |
| 中文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SDIP-42 |
| 文件頁(yè)數(shù)： | 17/92頁(yè) |
| 文件大?。?/td> | 382K |
| 代理商： | P83C566BDR |
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1999 Mar 10
17
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
10 I
2
C-BUS SERIAL I/O
10.1
The I
2
C-bus
The serial port supports the two line I
2
C-bus. The I
2
C-bus
consists of a serial data line (SDA) and a serial clock line
(SCL). These lines can also function as I/O port lines
P1.6 and P1.5 respectively. To utilize this facility pins
P1.5/SCL and P1.6/SDA must be configured as alternative
functions instead of port lines; see Section 10.8.
The system is unique because data transport, clock
generation, address recognition and bus control arbitration
are all controlled by hardware.
Full details of the I
2
C-bus are given in the document
“The I
2
C-bus and how to use it” This document may be
ordered using the code 9398 393 40011.
10.2
Operation modes
The I
2
C-bus serial I/O has complete autonomy in byte
handling and operates in four modes
Master transmitter
Master receiver
Slave transmitter
Slave receiver.
These functions are controlled by the S1CON register.
S1STA is the status register whose contents may also be
used as a vector to various service routines. S1DAT is the
data shift register and S1ADR the slave address register.
Slave address recognition is performed by hardware.
Fig.9 Block diagram of I
2
C-bus serial I/O.
handbook, full pagewidth
MBC749 - 1
SLAVE ADDRESS
S1ADR
GC
SHIFT REGISTER
S1DAT
SDA
ARBITRATION LOGIC
SCL
BUS CLOCK GENERATOR
S1STA
I
7
6
5
4
3
2
1
0
S1CON
7
6
5
4
3
2
1
0
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