參數(shù)資料
型號(hào)： P83C562EHA
廠商： NXP Semiconductors N.V.
元件分類： 8位微控制器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8位微控制器
文件頁(yè)數(shù)： 40/52頁(yè)
文件大?。?/td> 299K
代理商： P83C562EHA
1997 Apr 08
40
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
Notes to the DC characteristics
1.
The operating supply current is measured with all output pins disconnected;
XTAL1 driven with t
r
= t
f
= 10 ns; V
IL
= V
SS
+ 0.5 V; V
IH
= V
DD
0.5 V; XTAL2 not connected;
EA = RST = Port 0 = EW = V
DD
; STADC = V
SS
.
2.
The Idle mode supply current is measured with all output pins disconnected;
XTAL1 driven with t
r
= t
f
= 10 ns; V
IL
= V
SS
+ 0.5 V; V
IH
= V
DD
0.5 V; XTAL2 not connected;
EA = Port 0 = EW = V
DD
; RST = STADC = V
SS
.
3.
The Power-down current is measured with all output pins disconnected; XTAL2 not connected;
EA = Port 0 = EW = V
DD
; RST = STADC = XTAL1 = V
SS
.
4.
Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the low level output
voltage of ALE and Ports 1, 3 and 4. The noise is due to external bus capacitance discharging into the Port 0 and
Port 2 pins when these pins make HIGH-to-LOW transitions during bus operations. In the most adverse condition
(capacitive loading
>
100 pF), the noise pulse on the ALE line may exceed 0.8 V. In such events it may be required
to qualify ALE with a Schmitt trigger, or use an address latch with a Schmitt trigger strobe input.
5.
Capacitive loading on Ports 0 and 2 may cause the high level output voltage on ALE and PSEN to momentarily fall
below to 0.9V
DD
specification when the address bits are stabilizing.
6.
V
REF+
= 5.12 V; V
REF
= 0 V; V
DDA
= 5.0 V.
7.
The differential non-linearity (DL
e
) is the difference between the actual step width and the ideal step width.
8.
The integral non-linearity (IL
e
) is the peak difference between the centre of the steps of the actual and the ideal
transfer curve after appropriate adjustment of gain and offset error.
9.
The gain error (G
e
) is the relative difference in percent between the straight line fitting the actual transfer curve after
removing offset error, and the straight line which fits the ideal transfer curve. Gain error is constant at every point on
the transfer curve.
10. The offset error (OS
e
) is the absolute difference between the straight line which fits the actual transfer curve after
removing gain error, and a straight line which fits the ideal transfer curve. The offset error is constant at every point
of the actual transfer curve.
11. V
REF
= 0 V; V
DDA
= 5 V; V
REF+
= 5.12 V. The ADC is monotonic with no missing codes. Measurement by
continuously increasing V
IN
from
20 mV to 5.12 V in increments of 2 mV.
Analog inputs
V
IN
V
REF+
V
REF
R
REF
C
IA
t
ADS
t
ADC
analog input voltage
reference voltage (+)
reference voltage (
)
resistance between V
REF+
and V
REF
analog input capacitance
sampling time
conversion time
(including sample time)
differential non-linearity
integral non-linearity
offset error
gain error
channel-to-channel matching
crosstalk between P5 inputs
AV
SS
0.2
AV
SS
0.2
5
AV
DD
+ 0.2
AV
DD
+ 0.2
25
15
6t
CY
24t
CY
V
V
V
k
pF
μ
s
μ
s
DL
e
IL
e
OS
e
G
e
M
ctc
C
t
notes 7 and 11
notes 6 and 8
notes 6 and 10
notes 6 and 9
±
1
±
1
±
1
±
0.4
±
1
60
LSB
LSB
LSB
%
LSB
dB
0 to 100 kHz
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
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