1997 Apr 08
9
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
7
FUNCTIONAL DESCRIPTION
The P8xC562 is a stand-alone high-performance
microcontroller designed for use in real-time applications
such as instrumentation, industrial control and specific
automotive control applications.
In addition to the 80C51 standard functions, the device
provides a number of dedicated hardware functions for
these applications.
The P8xC562 is a control-oriented CPU with on-chip
program and data memory. It can be extended with
external program memory up to 64 kbytes. It can also
access up to 64 kbytes of external data memory.
For systems requiring extra capability, the P8xC562 can
be expanded using standard memories and peripherals.
The P8xC562 has two software selectable modes of
reduced activity for further power reduction
Idle and
Power-down. The Idle mode freezes the CPU while
allowing the RAM, timers, serial ports and interrupt system
to continue functioning. The Power-down mode saves the
RAM contents but freezes the oscillator causing all other
chip functions to be inoperative.
8
MEMORY ORGANIZATION
The Central Processing Unit (CPU) manipulates operands
in three memory spaces; these are the 64 kbyte external
data memory, 256 byte internal data memory and the
64 kbyte internal and external program memory.
The internal data memory is divided into 3 sections: the
lower 128 bytes of RAM, the upper 128 bytes of RAM and
the 128 byte Special Function Register memory
(see Fig.4). Figure 5 shows the Special Function
Registers memory map. Internal RAM locations 0 to 127
are directly and indirectly addressable. Internal RAM
locations 128 to 155 are only indirectly addressable.
The Special Function Register locations 128 to 255 are
only directly addressable.
The internal data RAM contains four register banks (each
with eight registers), 128 addressable bits, a scratch pad
area and the stack. The stack depth is limited by the
available internal data RAM and its location is determined
by the 8-bit Stack Pointer. All registers except the Program
Counter and the four 8-register banks reside in the
Special Function Register address space. These memory
mapped registers include arithmetic registers, pointers,
I/O ports, interrupt system registers, ADC and PWM
registers, timers and serial port registers. There are
120 addressable bit locations in the SFR address space.
The P8xC562 contains 256 bytes of internal data RAM
and 52 Special Function Registers. It provides a
non-paged program memory address space to
accommodate relocatable code. Conditional branches are
performed relative to the Program Counter.
The register-indirect jump permits branching relative to a
16-bit base register with an offset provided by an 8-bit
index register. 16-bit jumps and calls permit branching to
any location in the contiguous 64 kbyte program memory
address space.
8.1
Program Memory
The program memory address space of the P83C562
consists of internal and external memory. The P83C562
has 8 kbytes of program memory on-chip. The program
memory can be externally expanded up to 64 kbytes. If the
EA pin is held HIGH, the P83C562 executes out of the
internal program memory unless the address exceeds
1FFFH then locations 2000H through to 0FFFFH are
fetched from the external program memory. If the EA pin is
held LOW, the P83C562 fetches all instructions from the
external memory. Figure 4 illustrates the program
memory address space.
By setting a mask programmable security bit (i.e. user
dependent) the ROM content is protected i.e. it cannot be
read at any time by any test mode or by any instruction in
the external program memory space. The MOVC
instructions are the only ones which have access to
program code in the internal or external program memory.
TheEA input is latched during reset and is ‘don’t care’ after
reset. This implementation prevents from reading internal
program code by switching from the external program
memory to internal program memory during MOVC
instruction or an instruction that handles immediate data.
Table 2 lists the access to internal and external program
memory by the MOVC instructions when the security bit
has been set to a logic 1. If the security bit has been set to
a logic 0 there are no restrictions for the MOVC
instructions.
Table 2
Memory access by the MOVC instruction
MOVC
INSTRUCTION
PROGRAM MEMORY ACCESS
INTERNAL
EXTERNAL
MOVC in internal
program memory
MOVC in external
program memory
YES
YES
NO
YES